It was only being used by instructions with the t_addrmode_sp addressing mode,
and that is pattern matched in a way that guarantees SP is used. There is
never any register allocation done from this class.

llvm-svn: 93280

Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg.

For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used.

llvm-svn: 93278

llvm-svn: 93245

on x86-64 linux with messages like this:
Error: Incorrect register `%r14' used with `l' suffix

llvm-svn: 93242

llvm-svn: 93235

to not touch Cygwin: the change caused llvm-gcc build failures due to
long double getting the wrong size.  Patch by Aaron Gray.

llvm-svn: 93234

llvm-svn: 93229

instruction is copy like where the source and destination registers can
overlap. This is to be used by the coalescable to coalesce the source and
destination registers of instructions like X86::MOVSX64rr32. Apparently
some crazy people believe the coalescer is too simple.

llvm-svn: 93210

Add manual ISD::OR fastisel selection routines. TableGen is no longer autogen them after 93152 and 93191.

llvm-svn: 93204

Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead.

llvm-svn: 93191

llvm-svn: 93185

llvm-svn: 93182

- getToken is modeled after StringRef::split but it can split on multiple
  separator chars and skips leading seperators.
- SplitString is a StringRef::split variant for more than 2 elements with the
  same behaviour as getToken.

llvm-svn: 93161

has an immediate with at least 32 bits of leading zeros, to avoid needing to
materialize that immediate in a register first.

FileCheckize, tidy, and extend a testcase to cover this case.

This fixes rdar://7527390.

llvm-svn: 93160

new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.

llvm-svn: 93158

single user. The _su forms are intended for non-top-level nodes.

llvm-svn: 93155

llvm-svn: 93154

Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed.

llvm-svn: 93152

Implement a feature (-vector-unaligned-mem) to allow targets to
ignore alignment requirements for SIMD memory operands.  This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.

llvm-svn: 93151

"In order to ease automatic bindings generation, it would be helpful if boolean values were distinguishable from integers. The attached patch introduces "typedef int LLVMBool;", and uses LLVMBool instead of int throughout the C API, wherever a boolean value is called for."

Patch by James Y Knight!

llvm-svn: 93079

R11, and then asserting that the target was in R9.  Since R9 isn't reserved for
the target anymore, and is used as an argument, this patch changes the
assertion.

llvm-svn: 93065

Fix a critical bug in 64-bit atomic operation lowering for 32-bit. The results of the cmpxchg8b instructions are being thrown away when it branches back to the top of the checking loop. This means the loop always compares against the old value and this can result in a dead lock.

llvm-svn: 93028

llvm-svn: 93020

T2I_bin_ii12rs definition.

llvm-svn: 93006

putting relocations into the constant pool - this isn't needed
for correctness and in the rare occasion it happens would pull
us out of fast isel for the block.

If fast-isel application startup time ever becomes an issue we
can add better support for these addresses instead of bailing.

llvm-svn: 92995

1. CMPXCHG8B and CMPXCHG16B did not specify implicit physical register defs and uses.
2. LCMPXCHG8B is loading 64 bit memory, not 32 bit.

llvm-svn: 92985

llvm-svn: 92972

add it to the constant pool for fast-isel. We already
don't add it for the normal case.

llvm-svn: 92934

not-readonly segment on darwin.

llvm-svn: 92933

llvm-svn: 92921

Fix a minor regression from my dag combiner changes. One more place which needs to look pass truncates.

llvm-svn: 92885

llvm-svn: 92876

Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.

llvm-svn: 92873

for stack references.

llvm-svn: 92871

(OP (trunc x), (trunc y)) -> (trunc (OP x, y))

Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.

This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.

llvm-svn: 92849

phi nodes when deciding which pointers point to local memory.
I actually checked long ago how useful this is, and it isn't
very: it hardly ever fires in the testsuite, but since Chris
wants it here it is!

llvm-svn: 92836

memcpy, memset and other intrinsics that only access their arguments
to be readnone if the intrinsic's arguments all point to local memory.
This improves the testcase in the README to readonly, but it could in
theory be made readnone, however this would involve more sophisticated
analysis that looks through the memcpy.

llvm-svn: 92829

bootstrap.

llvm-svn: 92818

synonyms for PPC.

llvm-svn: 92817

llvm-svn: 92796