llvm-svn: 163059

llvm-svn: 163058

llvm-svn: 163053

llvm-svn: 163051

llvm-svn: 163049

llvm-svn: 163041

llvm-svn: 163040

output chain is correctly setup.

As an example, if the original load must happen before later stores, we need
to make sure the constructed VZEXT_LOAD is constrained to be before the stores.

rdar://11457792

llvm-svn: 163036

llvm-svn: 163035

Patch by Brad Smith!

llvm-svn: 163033

function nowadays.

llvm-svn: 163030

llvm-svn: 163029

Manage tied operands entirely internally to MachineInstr. This makes it
possible to change the representation of tied operands, as I will do
shortly.

The constraint that tied uses and defs must be in the same order was too
restrictive.

llvm-svn: 163021

- In addition to undefined, if V2 is zero vector, skip 2nd PSHUFB and POR as
  well as PSHUFB will zero elements with negative indices.

  Patch by Sriram Murali <sriram.murali@intel.com>

llvm-svn: 163018

on the size of the extraction and its position in the 64 bit word.

This patch allows support of the dext transformations with mips64 direct
object output.

0 <= msb < 32 0 <= lsb < 32 0 <= pos < 32 1 <= size <= 32
DINS
The field is entirely contained in the right-most word of the doubleword

32 <= msb < 64 0 <= lsb < 32 0 <= pos < 32 2 <= size <= 64
DINSM
The field straddles the words of the doubleword

32 <= msb < 64 32 <= lsb < 64 32 <= pos < 64 1 <= size <= 32
DINSU
The field is entirely contained in the left-most word of the doubleword

llvm-svn: 163010

llvm-svn: 163008

llvm-svn: 163005

llvm-svn: 163002

llvm-svn: 163001

Use CloneMachineInstr to make a new MI in commuteInstruction to make the code tolerant of instructions with more than two input operands.

llvm-svn: 163000

llvm-svn: 162999

I was too optimistic, inline asm can have tied operands that don't
follow the def order.

Fixes PR13742.

llvm-svn: 162998

- Overloading operator<< for raw_ostream and pointers is dangerous, it alters
  the behavior of code that includes the header.
- Remove unused ID.
- Use LLVM's byte swapping helpers instead of a hand-coded.
- Make ReadProfilingData work directly on a pointer.

No functionality change.

llvm-svn: 162992

FIXME: Should this be tested with both +avx and -avx,+sse2?
llvm-svn: 162983

llvm-svn: 162979

llvm-svn: 162973

Thumb2 instructions are mostly constrained to rGPR, not tGPR which is
for Thumb1.

rdar://problem/12203728

llvm-svn: 162968

The assembly string for the VMOVPQIto64rr instruction incorrectly lacked the 'v'
prefix, resulting in mis-assembly of the vanilla movd instruction.

llvm-svn: 162963

the ConvertToMCInst() return void, rather then a bool.  Update all the cvt
functions as well.

llvm-svn: 162961

Take account of boolean vector contents when promoting a build vector from i1 to some other type.  rdar://problem/12210060

llvm-svn: 162960

llvm-svn: 162958

Teach the DAG combiner to turn chains of FADDs (x+x+x+x+...) into FMULs by constants.  This is only enabled in unsafe FP math mode, since it does not preserve rounding effects for all such constants.

llvm-svn: 162956

llvm-svn: 162955

llvm-svn: 162954

llvm-svn: 162953

llvm-svn: 162952

llvm-svn: 162946

llvm-svn: 162945

an 80-column violation in the generated code.  No functional change intended.

llvm-svn: 162944

Currently targets that do not support selects with scalar conditions and vector operands - scalarize the code. ARM is such a target
because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR
to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2).

rdar://12201387

llvm-svn: 162926