llvm-svn: 39843

Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.

llvm-svn: 39816

llvm-svn: 39813

following jump tables that it earlier inserted.  This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).

llvm-svn: 39782

llvm-svn: 39772

Fixed print immediate 
Fixed Identation on MipsISelDAGToDAG.cpp

llvm-svn: 39764

Prologue/Epilogue support fp,ra save/restore and use the stack frame the right
way!

llvm-svn: 39763

llvm-svn: 39761

FI's created the write way to represent Mips stack

llvm-svn: 39760

llvm-svn: 39759

llvm-svn: 39758

llvm-svn: 39752

of size other than 4).

llvm-svn: 39743

llvm-svn: 39737

the sparc backend should be preferred when running on sparcs.

llvm-svn: 39142

llvm-svn: 38515

llvm-svn: 38514

llvm-svn: 38513

pedantic satisfaction level.

llvm-svn: 38512

llvm-svn: 38507

llvm-svn: 38501

llvm-svn: 38500

in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.

llvm-svn: 38478

register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.

llvm-svn: 38471

zero if they see a target triple they don't understand.

llvm-svn: 38463

llvm-svn: 37965

llvm-svn: 37962

llvm-svn: 37961

llvm-svn: 37960

llvm-svn: 37959

llvm-svn: 37940

llvm-svn: 37932

llvm-svn: 37931

llvm-svn: 37930

llvm-svn: 37926

llvm-svn: 37923

llvm-svn: 37917

llvm-svn: 37915

llvm-svn: 37914

Almost all occurrences of "bytecode" in the sources have been eliminated.

llvm-svn: 37913