instruction.

This can happen on ARM:

>> %reg1035:5<def>, %reg1035:6<def> = VLD1q16 %reg1028, 0, pred:14, pred:%reg0
Regs: Q0=%reg1032* R0=%reg1028* R1=%reg1029* R2 R3=%reg1031*
Killing last use: %reg1028
Allocating %reg1035 from QPR
Assigning %reg1035 to Q1
<< %D2<def>, %D3<def> = VLD1q16 %R0<kill>, 0, pred:14, pred:%reg0, %Q1<imp-def>

llvm-svn: 104056

Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.

llvm-svn: 104051

Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.

llvm-svn: 104050

CurPtr[0] == '\n' when testing the character after a "0b" when looking
to see if it part of a something like "jmp 0b".

llvm-svn: 104039

correctly.  The Lexer was incorrectly eating the newline casusing it to branch
to address 0.  Updated the test case to use a "0:" label and a branch to "0b".

llvm-svn: 104038

The old approach was wrong. It had an off-by-one error.

llvm-svn: 104034

Also, create symbol data for LHS of assignment, to match 'as' symbol ordering better.

llvm-svn: 104033

llvm-svn: 104032

llvm-svn: 104031

  X86::ADC32ri $0, %eax
to
  X86::ADC32i32 $0

llvm-svn: 104030

llvm-svn: 104029

Update the comment.

llvm-svn: 104021

- Allocate MCLabels in the context so they don't leak.
- Avoid duplicated densemap lookup.

llvm-svn: 104020

FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)). 

llvm-svn: 104004

too large limit.

The function would return immediately when finding an addrmode 3/5 instruction.
It needs to keep scanning in case there is an addrmode 6 instruction which drops
the limit to 0.

A test case is very difficult to produce because it will only fail when the
scavenger is used.

rdar://problem/7894847

llvm-svn: 103995

Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions.

llvm-svn: 103994

- Change the logic DisableFramePointerElim() to check for the
  -disable-non-leaf-fp-elim before -disable-fp-elim.

llvm-svn: 103990

llvm-svn: 103989

and cleanup comments as well.

llvm-svn: 103985

Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def.

llvm-svn: 103984

llvm-svn: 103982

MC/Mach-O/x86: Optimal nop sequences should only be used for the .text sections, not all sections in the text segment.

llvm-svn: 103981

 - Of questionable utility, since in general anything which wants to do this should probably be within a target specific hook, which can rely on the sections being of the appropriate type. However, it can be useful for short term hacks.

llvm-svn: 103980

 - This fixes a string table mismatch with 'as' when two new symbols are defined
   in a single instruction.

llvm-svn: 103979

This fixes the miscompilations of MultiSource/Applications/JM/l{en,de}cod.
Clang now successfully self hosts in a debug build with the fast register allocator.

llvm-svn: 103975

llvm-svn: 103974

llvm-svn: 103971

Obvious in retrospect but not fun to debug.

llvm-svn: 103969

 - Don't clear weak reference flag, 'as' was only "trying" to do this, it wasn't
   actually succeeding.
 - Clear the "lazy bound" bit when we mark something external. This corresponds
   roughly to the lazy clearing of the bit that 'as' implements in
   symbol_table_lookup.
 - The exact meaning of these flags appears pretty loose, since 'as' isn't very
   consistent. For now we just try to match 'as', we will clean this up one day
   hopefully.

llvm-svn: 103964

llvm-svn: 103961

Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!

llvm-svn: 103960

variable has not yet been used in an expression. This allows us to support a few
cases that show up in real code (mostly because gcc generates it for Objective-C
on Darwin), without giving up a reasonable semantic model for assignment.

llvm-svn: 103950

While that approach works wonders for register pressure, it tends to break
everything.

This should unbreak the arm-linux builder and fix a number of miscompilations.

llvm-svn: 103946

llvm-svn: 103940

out aliases when allocating. Clean up allocVirtReg().

Use calcSpillCost() to allow more aggressive hinting. Now the hint is always
taken unless blocked by a reserved register. This leads to more coalescing,
lower register pressure, and less spilling.

llvm-svn: 103939

llvm-svn: 103936

This makes allocation independent on the ordering of use-def chains.

llvm-svn: 103935

llvm-svn: 103934

This is safe to do because the physreg has been marked UsedInInstr and the kill flag will be set on the last operand using the virtreg if there are more then one.

llvm-svn: 103933

llvm-svn: 103931