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  1. Jul 19, 2009
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  4. Jul 16, 2009
    • Jakob Stoklund Olesen's avatar
      Silence warning in Linux builds: · c7895d3c
      Jakob Stoklund Olesen authored
      X86InstrInfo.cpp:2272: warning: suggest explicit braces to avoid ambiguous 'else'
      
      llvm-svn: 76105
      c7895d3c
    • Jeffrey Yasskin's avatar
      Add line numbers to OProfile. To do this, I added a processDebugLoc() · efad8e45
      Jeffrey Yasskin authored
      call to the MachineCodeEmitter interface and made copying the start
      line of a function not conditional on whether we're emitting Dwarf
      debug information. I'll propagate the processDebugLoc() calls to the
      non-X86 targets in a followup patch.
      
      In the long run, it'll probably be better to gather this information
      through the DwarfWriter, but the DwarfWriter currently depends on the
      AsmPrinter and TargetAsmInfo, and fixing that would be out of the way
      for this patch.
      
      There's a bug in OProfile 0.9.4 that makes it ignore line numbers for
      addresses above 4G, and a patch fixing it at
      http://thread.gmane.org/gmane.linux.oprofile/7634
      
      Sample output:
      
      $ sudo opcontrol --reset; sudo opcontrol --start-daemon; sudo opcontrol --start; `pwd`/Debug/bin/lli fib.bc; sudo opcontrol --stop
      Signalling daemon... done
      Profiler running.
      fib(40) == 165580141
      Stopping profiling.
      
      $ opreport -g -d -l `pwd`/Debug/bin/lli|head -60
      Overflow stats not available
      CPU: Core 2, speed 1998 MHz (estimated)
      Counted CPU_CLK_UNHALTED events (Clock cycles when not halted) with a unit mask of 0x00 (Unhalted core cycles) count 100000
      vma      samples  %        linenr info                 image name               symbol name
      00007f67a30370b0 25489    61.2554  fib.c:24                    10946.jo                 fib_left
        00007f67a30370b0 1634      6.4106  fib.c:24
        00007f67a30370b1 83        0.3256  fib.c:24
        00007f67a30370b9 1997      7.8348  fib.c:24
        00007f67a30370c6 2080      8.1604  fib.c:27
        00007f67a30370c8 988       3.8762  fib.c:27
        00007f67a30370cd 1315      5.1591  fib.c:27
        00007f67a30370cf 251       0.9847  fib.c:27
        00007f67a30370d3 1191      4.6726  fib.c:27
        00007f67a30370d6 975       3.8252  fib.c:27
        00007f67a30370db 1010      3.9625  fib.c:27
        00007f67a30370dd 242       0.9494  fib.c:27
        00007f67a30370e1 2782     10.9145  fib.c:28
        00007f67a30370e5 3768     14.7828  fib.c:28
        00007f67a30370eb 615       2.4128  (no location information)
        00007f67a30370f3 6558     25.7287  (no location information)
      00007f67a3037100 15603    37.4973  fib.c:29                    10946.jo                 fib_right
        00007f67a3037100 1646     10.5493  fib.c:29
        00007f67a3037101 45        0.2884  fib.c:29
        00007f67a3037109 2372     15.2022  fib.c:29
        00007f67a3037116 2234     14.3178  fib.c:32
        00007f67a3037118 612       3.9223  fib.c:32
        00007f67a303711d 622       3.9864  fib.c:32
        00007f67a303711f 385       2.4675  fib.c:32
        00007f67a3037123 404       2.5892  fib.c:32
        00007f67a3037126 634       4.0633  fib.c:32
        00007f67a303712b 870       5.5759  fib.c:32
        00007f67a303712d 62        0.3974  fib.c:32
        00007f67a3037131 1848     11.8439  fib.c:33
        00007f67a3037135 2840     18.2016  fib.c:33
        00007f67a303713a 1         0.0064  fib.c:33
        00007f67a303713b 1023      6.5564  (no location information)
        00007f67a3037143 5         0.0320  (no location information)
      000000000080c1e4 15        0.0360  MachineOperand.h:150        lli                      llvm::MachineOperand::isReg() const
        000000000080c1e4 6        40.0000  MachineOperand.h:150
        000000000080c1ec 2        13.3333  MachineOperand.h:150
      ...
      
      llvm-svn: 76102
      efad8e45
    • Evan Cheng's avatar
      With recent MC changes, RIP base register is explicitly modeled. Make sure we... · fdd0eb40
      Evan Cheng authored
      With recent MC changes, RIP base register is explicitly modeled. Make sure we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction.
      
      llvm-svn: 76094
      fdd0eb40
    • Anton Korobeynikov's avatar
      Unbreak · 02fc607d
      Anton Korobeynikov authored
      llvm-svn: 76064
      02fc607d
    • Anton Korobeynikov's avatar
      Temporary disable 16 bit bswap · 73fcd3d9
      Anton Korobeynikov authored
      llvm-svn: 76063
      73fcd3d9
    • Anton Korobeynikov's avatar
      Add instruction formats and few opcodes · 460e5903
      Anton Korobeynikov authored
      llvm-svn: 76062
      460e5903
    • Anton Korobeynikov's avatar
      Add bswap patterns · 902facfe
      Anton Korobeynikov authored
      llvm-svn: 76061
      902facfe
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