All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms.
Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors.
Added lowering for EXTRACT/INSERT subvector for 512-bit vectors.
Added a test.

llvm-svn: 187491

Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax.

Patch by Richard Mitton.

llvm-svn: 187476

llvm-svn: 187472

Patch by Richard Mitton.

llvm-svn: 187471

Win64 uses CharPtrBuiltinVaList instead of X86_64ABIBuiltinVaList like
other 64-bit targets.

llvm-svn: 187355

Added 512-bit operands printing.
Added instruction formats for KNL instructions.

llvm-svn: 187324

CustomLowerNode was not being called during SplitVectorOperand,
meaning custom legalization could not be used by targets.

This also adds a test case for NVPTX that depends on this custom
legalization.

Differential Revision: http://llvm-reviews.chandlerc.com/D1195

Attempt to fix the buildbots by making the X86 test I just added platform independent

llvm-svn: 187202

This reverts commit 187198. It broke the bots.

The soft float test probably needs a -triple because of name differences.
On the hard float test I am getting a "roundss $1, %xmm0, %xmm0", instead of
"vroundss $1, %xmm0, %xmm0, %xmm0".

llvm-svn: 187201

CustomLowerNode was not being called during SplitVectorOperand,
meaning custom legalization could not be used by targets.

This also adds a test case for NVPTX that depends on this custom
legalization.

Differential Revision: http://llvm-reviews.chandlerc.com/D1195

llvm-svn: 187198

llvm-svn: 187187

llvm-svn: 187182

I'm starting to commit KNL backend. I'll push patches one-by-one. This patch includes support for the extended register set XMM16-31, YMM16-31, ZMM0-31.
The full ISA you can see here: http://software.intel.com/en-us/intel-isa-extensions

llvm-svn: 187030

This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o.

llvm-svn: 187026

Fix aliases for shrd/shld to handle Intel syntax properly. Also suppress them from being used by the asm printer.

llvm-svn: 187020

llvm-svn: 186932

llvm-svn: 186924

llvm-svn: 186910

llvm-svn: 186907

This makes them consistent with 'bt' which already had this handling. gas has the same behavior. There have been discussions on the mailing list about determining size based on the immediate, but my goal here was just to remove the inconsistency.

llvm-svn: 186904

It only didn't use it before because it seems InstAlias handling in the asm printer fails to count tied operands so it tried to find an xor with 2 operands instead of the 3 it wfails to count tied.

llvm-svn: 186900

Suppress argumentless aliases for some x86 FP operations from being used by the asm writer. Prefer to use the explicit %st(1) form.

llvm-svn: 186897

absolute address encoded in the instruction.

rdar://8612627 and rdar://14299221

llvm-svn: 186878

Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer.

llvm-svn: 186869

This reverts commit r186813, which broke the bots.

llvm-svn: 186818

llvm-svn: 186815

llvm-svn: 186814

llvm-svn: 186813

llvm-svn: 186812

llvm-svn: 186811

llvm-svn: 186809

llvm-svn: 186787

llvm-svn: 186566

llvm-svn: 186496

Make x86 fast-isel correctly choose between aligned and unaligned operations for vector stores. Fixes PR16640.

llvm-svn: 186491

Use PMIN/PMAX for UGE/ULE vector comparions to reduce the number of required
instructions. This trick also works for UGT/ULT, but there is no advantage in
doing so. It wouldn't reduce the number of instructions and it would actually
reduce performance.

Reviewer: Ben

radar:5972691

llvm-svn: 186432

llvm-svn: 186308

llvm-svn: 186274

radar://14351991

llvm-svn: 186189

In particular:
movsbw %al, %ax   --> cbtw
movswl %ax, %eax  --> cwtl
movslq %eax, %rax --> cltq

According to Intel's manual those have the same performance characteristics but
come with a smaller encoding.

llvm-svn: 186174

Patch by Andrea Di Biagio

llvm-svn: 186165