llvm-svn: 29228

llvm-svn: 29215

llvm-svn: 29214

llvm-svn: 29213

llvm-svn: 29210

As such, use xoaddr (indexed only), not xaddr for address selection.

This fixes CodeGen/PowerPC/2006-07-19-stwbrx-crash.ll, a crash compiling lencod.

llvm-svn: 29208

Missing Darwin check in Intel ATT ASM printer.

llvm-svn: 29204

llvm-svn: 29202

llvm-svn: 29194

llvm-svn: 29193

llvm-svn: 29175

llvm-svn: 29174

llvm-svn: 29159

complete.

llvm-svn: 29156

llvm-svn: 29153

llvm-svn: 29140

llvm-svn: 29139

the same.

llvm-svn: 29136

when using the immshifted addressing mode.

llvm-svn: 29130

llvm-svn: 29128

llvm-svn: 29125

function instead of returning a value.  This sometimes allowed the ppc32 jit
to be used in 64-bit mode.

llvm-svn: 29123

This implements PR828 and CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll

llvm-svn: 29118

llvm-svn: 29114

llvm-svn: 29110

llvm-svn: 29106

non-debug build.

llvm-svn: 29105

this makes it possible for ldr instructions with non-zero immediate

llvm-svn: 29103

CodeGen/X86/2006-07-10-InlineAsmAConstraint.ll

llvm-svn: 29101

llvm-svn: 29096

llvm-svn: 29091

Use that information when doing the transformation to merge multiple loads
into a 128-bit load.

llvm-svn: 29090

into i16/i32 load/stores.

llvm-svn: 29089

llvm-svn: 29085

use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot

llvm-svn: 29079

llvm-svn: 29072

(load x+8), (load x+12), <0, 1, 2, 3> to a single 128-bit load (aligned and
unaligned).

e.g.

__m128 test(float a, float b, float c, float d) {
  return _mm_set_ps(d, c, b, a);
}

_test:
        movups 4(%esp), %xmm0
        ret

llvm-svn: 29042

llvm-svn: 29011

values include small, kernel, medium, large, and default.

llvm-svn: 29009

llvm-svn: 28999