Commits · 686d33fd62e832795c48573002c77e9910c8c2eb · Roger Ferrer / llvm-epi-0.8

Jun 07, 2013
- R600: Rewrite an awkward loop in R600MachineScheduler · 0030362e
  Vincent Lejeune authored Jun 06, 2013
```
llvm-svn: 183458
```
  0030362e
Jun 06, 2013
- Revert "ARM sched model: Add SIMD/VFP load/store instructions on Swift" · e5f6a8f6
  Arnold Schwaighofer authored Jun 06, 2013
```
Breaks linux build bots (I thought the problem was something else).

llvm-svn: 183447
```
  e5f6a8f6
- ARM sched model: Add SIMD/VFP load/store instructions on Swift · cfe830dc
  Arnold Schwaighofer authored Jun 06, 2013
```
Reapply 183270.

llvm-svn: 183445
```
  cfe830dc
- ARM sched model: Add integer VFP/SIMD instructions on Swift · eac54473
  Arnold Schwaighofer authored Jun 06, 2013
```
Reapply 183269.

llvm-svn: 183441
```
  eac54473
- ARM sched model: Add integer load/store instructions on Swift · dff8e4c4
  Arnold Schwaighofer authored Jun 06, 2013
```
Reapply 183268.

llvm-svn: 183438
```
  dff8e4c4
- ARM sched model: Add integer arithmetic instructions on Swift · 41a7b068
  Arnold Schwaighofer authored Jun 06, 2013
```
Reapply 183267.

llvm-svn: 183436
```
  41a7b068
- ARM sched model: Cortex A9 - More InstRW sched resources · 57142859
  Arnold Schwaighofer authored Jun 06, 2013
```
Add more InstRW mappings.

Reapply 183266.

llvm-svn: 183435
```
  57142859
- ARM sched model: Add branch thumb instructions · f1395b69
  Arnold Schwaighofer authored Jun 06, 2013
```
Reapply 183265.

llvm-svn: 183432
```
  f1395b69
- ARM sched model: Add branch thumb2 instructions · 10ccc99c
  Arnold Schwaighofer authored Jun 06, 2013
```
Reapply 183264.

llvm-svn: 183430
```
  10ccc99c
- ARM sched model: Add branch instructions · 91d4ee37
  Arnold Schwaighofer authored Jun 06, 2013
```
Reapply 183263.

llvm-svn: 183428
```
  91d4ee37
- ARM sched model: Add preload thumb2 instructions · 57727977
  Arnold Schwaighofer authored Jun 06, 2013
```
Reapply 183262.

llvm-svn: 183427
```
  57727977
- ARM sched model: Add preload instructions · 1b413304
  Arnold Schwaighofer authored Jun 06, 2013
```
Reapply 183261.

llvm-svn: 183425
```
  1b413304
- ARM sched model: Add more ALU and CMP thumb instructions · 654649dd
  Arnold Schwaighofer authored Jun 06, 2013
```
Reapply of 183260.

llvm-svn: 183423
```
  654649dd
- ARM sched model: Add more ALU and CMP thumb2 instructions · 972ce477
  Arnold Schwaighofer authored Jun 06, 2013
```
Reapply of 183259.

llvm-svn: 183421
```
  972ce477
- R600: Remove leftover code in R600MachineScheduler.cpp · 54476a15
  Vincent Lejeune authored Jun 06, 2013
```
Spotted by Benjamin Kramer.

llvm-svn: 183413
```
  54476a15
- Cast to the correct type. Pointer, not reference. · b9121681
  Bill Wendling authored Jun 06, 2013
```
llvm-svn: 183385
```
  b9121681
- R600OptimizeVectorRegisters.cpp: Tweak a warning. [-Wsometimes-uninitialized] · 4a8f0793
  NAKAMURA Takumi authored Jun 06, 2013
```
FIXME: Is it false alarm?
llvm-svn: 183371
```
  4a8f0793
- R600OptimizeVectorRegisters.cpp: Suppress a warning. [-Wunused-variable] · e5555fc2
  NAKAMURA Takumi authored Jun 06, 2013
```
llvm-svn: 183370
```
  e5555fc2
- Trailing linefeed. · 372574d4
  NAKAMURA Takumi authored Jun 06, 2013
```
llvm-svn: 183369
```
  372574d4
- Cast to the proper type. · e4105768
  Bill Wendling authored Jun 06, 2013
```
llvm-svn: 183365
```
  e4105768
- Cache the TargetLowering info object as a pointer. · f7719085
  Bill Wendling authored Jun 06, 2013
```
Caching it as a pointer allows us to reset it if the TargetMachine object
changes.

llvm-svn: 183361
```
  f7719085
- R600: Replace predicate loop with predicate function · acec99c9
  Tom Stellard authored Jun 05, 2013
```
llvm-svn: 183351
```
  acec99c9
Jun 05, 2013
- R600: Add a pass that merge Vector Register · dec18752
  Vincent Lejeune authored Jun 05, 2013
```
Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.

llvm-svn: 183343
```
  dec18752
- R600: Schedule copy from phys register at beginning of block · 4b5b8497
  Vincent Lejeune authored Jun 05, 2013
```
It allows regalloc pass to remove them by trivially assigning associated reg

llvm-svn: 183336
```
  4b5b8497
- [mips] brcond + setgt/setugt instruction selection patterns. · da4496c8
  Akira Hatanaka authored Jun 05, 2013
```
llvm-svn: 183334
```
  da4496c8
- [PATCH] Fix VGATHER* operand constraints · 00b20cc9
  Michael Liao authored Jun 05, 2013
```
Add earlyclobber constaints to prevent input register being allocated as
the output register because, according to Intel spec [1], "If any pair
of the index, mask, or destination registers are the same, this
instruction results a UD fault."

---
[1] http://software.intel.com/sites/default/files/319433-014.pdf

llvm-svn: 183327
```
  00b20cc9
- ARM sched model: Add more ALU and CMP instructions · 81910d0e
  Arnold Schwaighofer authored Jun 05, 2013
```
Reapply of 183258.

llvm-svn: 183321
```
  81910d0e
- ARM sched model: Add divsion, loads, branches, vfp cvt · 2773f1de
  Arnold Schwaighofer authored Jun 05, 2013
```
Add some generic SchedWrites and assign resources for Swift and Cortex A9.

Reapply of r183257. (Removed empty InstRW for division on swift)

llvm-svn: 183319
```
  2773f1de
- ARMInstrInfo: Improve isSwiftFastImmShift · e937592e
  Arnold Schwaighofer authored Jun 05, 2013
```
An instruction with less than 3 inputs is trivially a fast immediate shift.

Reapply of 183256, should not have caused the tablegen segfault on linux either.

llvm-svn: 183314
```
  e937592e
- This is a simple patch that changes RRX and RRXS to accept all registers as operands. · 0e9892fe
  Mihai Popa authored Jun 05, 2013
```
According to the ARM reference manual, RRX(S) have defined encodings for lr, pc and sp.

llvm-svn: 183307
```
  0e9892fe
- R600: Make sure to schedule AR register uses and defs in the same clause · aad5376f
  Tom Stellard authored Jun 05, 2013
```
Reviewed-by: vljn at ovi.com
llvm-svn: 183294
```
  aad5376f
- Revert "R600: Add a pass that merge Vector Register" · beef23fe
  Rafael Espindola authored Jun 05, 2013
```
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.

llvm-svn: 183286
```
  beef23fe
- Handle relocations that don't point to symbols. · 806f0064
  Rafael Espindola authored Jun 05, 2013
```
In ELF (as in MachO), not all relocations point to symbols. Represent this
properly by using a symbol_iterator instead of a SymbolRef. Update llvm-readobj
ELF's dumper to handle relocatios without symbols.

llvm-svn: 183284
```
  806f0064
- R600: Add a pass that merge Vector Register · a45aafab
  Vincent Lejeune authored Jun 04, 2013
```
llvm-svn: 183279
```
  a45aafab
- R600: Const/Neg/Abs can be folded to dot4 · c6896791
  Vincent Lejeune authored Jun 04, 2013
```
llvm-svn: 183278
```
  c6896791
- Cortex-R5 can issue Thumb2 integer division instructions. · 4ec30970
  Evan Cheng authored Jun 04, 2013
```
llvm-svn: 183275
```
  4ec30970
- Revert series of sched model patches until I figure out what is going on. · 2a70c69d
  Arnold Schwaighofer authored Jun 04, 2013
```
llvm-svn: 183273
```
  2a70c69d
- ARM sched model: Add VFP div instruction on Swift · 0024b8bd
  Arnold Schwaighofer authored Jun 04, 2013
```
llvm-svn: 183271
```
  0024b8bd
- ARM sched model: Add SIMD/VFP load/store instructions on Swift · 89901730
  Arnold Schwaighofer authored Jun 04, 2013
```
llvm-svn: 183270
```
  89901730
- ARM sched model: Add integer VFP/SIMD instructions on Swift · bc61f091
  Arnold Schwaighofer authored Jun 04, 2013
```
llvm-svn: 183269
```
  bc61f091