llvm-svn: 95742

llvm-svn: 95740

register coalescing.  This fixes many crashes and
places where debug info affects codegen (when
dbg.value is lowered to machine instructions, which
it isn't yet in TOT).

llvm-svn: 95739

The major win of this is that the code is simpler and they 
print on the same line as the instruction again:

        movl    %eax, 96(%esp)          ## 4-byte Spill
        movl    96(%esp), %eax          ## 4-byte Reload
        cmpl    92(%esp), %eax          ## 4-byte Folded Reload
        jl      LBB7_86

llvm-svn: 95738

llvm-svn: 95737

llvm-svn: 95736

the field from being used uninitialized later in some cases.

llvm-svn: 95735

OutStreamer.AddBlankLine instead of textually.

llvm-svn: 95734

IntegerValType holds a uint32_t, so its constructor should take a uint32_t.  This allows it to be properly initialized with bit widths > 65535

llvm-svn: 95731

llvm-svn: 95730

prefix which is part of the opcode encoding.

llvm-svn: 95729

Enhance the x86 backend to show the hex values of immediates in
comments when they are large.  For example:

        movl    $1072693248, 4(%esp)    ## imm = 0x3FF00000

llvm-svn: 95728

TableGen fragment refactoring.

Move some utility TableGen defs, classes, etc. into a common file so
they may be used my multiple pattern files.  We will use this for
the AVX specification to help with the transition from the current
SSE specification.

llvm-svn: 95727

A8.6.279

llvm-svn: 95713

Only dump output in debug mode.

llvm-svn: 95711

llvm-mc: Add --show-fixups option, for displaying the instruction fixup information in the asm comments.

llvm-svn: 95710

llvm-svn: 95709

llvm-svn: 95708

llvm-svn: 95707

A8.6.335 & A8.6.336

llvm-svn: 95703

llvm-svn: 95699

in X86-32 mode.  This is still required in x86-64 mode to avoid
forming [disp+rip] encoding.  Rewrite the SIB byte decision logic
to be actually understandable.

llvm-svn: 95693

enable constant 0 offset lowering.

llvm-svn: 95691

a confusing idiom to check for ESP or RSP.

llvm-svn: 95690

llvm-svn: 95689

into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.

llvm-svn: 95686

consuming for a simple optimization.

llvm-svn: 95671

For disassembly only.

A8.6.300

llvm-svn: 95669

Patch by M Wahab!

llvm-svn: 95668

llvm-svn: 95650

llvm-svn: 95649

llvm-svn: 95647

llvm-svn: 95646

llvm-svn: 95643

xform.

llvm-svn: 95642

llvm-svn: 95641

	movl	$3735928559, a          ## inst: <MCInst 1273 <MCOperand Reg:0> <MCOperand Imm:1> <MCOperand Reg:0> <MCOperand Expr:(a)> <MCOperand Reg:0> <MCOperand Expr:(3735928559)>>

after:

	movl	$3735928559, a          ## <MCInst #1273
                                        ##   <MCOperand Reg:0>
                                        ##   <MCOperand Imm:1>
                                        ##   <MCOperand Reg:0>
                                        ##   <MCOperand Expr:(a)>
                                        ##   <MCOperand Reg:0>
                                        ##   <MCOperand Expr:(3735928559)>>

llvm-svn: 95637

Previously spill registers, whose def indexes are not defined, would sometimes be improperly marked as coalescable with conflicting registers. The new findCoalesces routine conservatively assumes that any register with at least one undefined def is not coalescable with any register it interferes with.

llvm-svn: 95636

llvm-svn: 95634