llvm-svn: 147232

DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.

llvm-svn: 147017

llvm-svn: 147004

llvm-svn: 147003

llvm-svn: 146995

patterns emit a single LUi instruction instead of a pair of LUi and ORi.

llvm-svn: 146900

direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.

llvm-svn: 146893

llvm-svn: 146889

llvm-svn: 146232

- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC. 
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
  substituted with other existing nodes.

llvm-svn: 146175

RDHWR. 

llvm-svn: 146101

llvm-svn: 146097

llvm-svn: 146096

llvm-svn: 146086

llvm-svn: 146059

PerformANDCombine and PerformOrCombine aware of them. Test cases are included
too.

llvm-svn: 145853

nodes.

llvm-svn: 144841

llvm-svn: 144840

llvm-svn: 144554

llvm-svn: 144448

llvm-svn: 144372

llvm-svn: 144370

llvm-svn: 144368

llvm-svn: 143994

when shift amount is larger than 32.

llvm-svn: 143990

instruction definitions.

llvm-svn: 143989

llvm-svn: 143988

llvm-svn: 142216

llvm-svn: 142214

llvm-svn: 142211

source registers and redefine 32-bit and 64-bit instructions.

llvm-svn: 142210

and have 32-bit and 64-bit instructions derive from it.

llvm-svn: 142207

llvm-svn: 142205

llvm-svn: 141761

instructions with two register operands derive from it.

llvm-svn: 141742

arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.

llvm-svn: 141736

the real instructions.

llvm-svn: 141718

llvm-svn: 141715

llvm-svn: 141708

llvm-svn: 141696