llvm-svn: 70546

llvm-svn: 70539

llvm-svn: 70537

gone lost during the pImpl conversion.

llvm-svn: 70536

llvm-svn: 70534

llvm-svn: 70533

llvm-svn: 70524

llvm-svn: 70522

-Replace DebugLocTuple's Source ID with CompileUnit's GlobalVariable*
-Remove DwarfWriter::getOrCreateSourceID
-Make necessary changes for the above (fix callsites, etc.)

llvm-svn: 70520

Don't include memory allocated for global variables during relocations resolution.

llvm-svn: 70517

llvm-svn: 70513

classes.

This is implemented as a function rather than a method on TargetRegisterClass
because it is symmetric in its arguments.

llvm-svn: 70512

llvm-svn: 70510

compute an upper-bound value for the trip count, in addition to
the actual trip count. Use this to allow getZeroExtendExpr and
getSignExtendExpr to fold casts in more cases.

This may eventually morph into a more general value-range
analysis capability; there are certainly plenty of places where
more complete value-range information would allow more folding.

llvm-svn: 70509

Add a smarter heuristic to determine when to coalesce a virtual register with a physical one. More specifically, it avoid tying a virtual register in the loop with a physical register defined / used outside the loop. When it determines it's not profitable, it will use the physical register as the allocation preference instead.

This is *not* turned on by default. Testing indicates this is just as likely to pessimize code. The main issue seems to be allocation preference doesn't work effectively. That will change once I've taught register allocator "swapping".

llvm-svn: 70503

in getSCEVAtScope.

llvm-svn: 70495

class.

llvm-svn: 70488

llvm-svn: 70466

a SCEVable type, not just integer types.

llvm-svn: 70463

llvm-svn: 70461

memory operands otherwise the writebacks get lost when the inline asm 
doesn't otherwise have side effects.  This fixes rdar://6839427, though
clang really shouldn't generate these anymore.

llvm-svn: 70455

llvm-svn: 70454

llvm-svn: 70453

which better identifies what the optimization is doing. And is more flexible for
future uses.

llvm-svn: 70440

llvm-svn: 70437

llvm-svn: 70427

llvm-svn: 70425

llvm-svn: 70422

(sext i8 {-128,+,1} to i64) to i64 {-128,+,1}, where the iteration
crosses from negative to positive, but is still safe if the trip
count is within range.

llvm-svn: 70421

llvm-svn: 70416

llvm-svn: 70408

print sext, zext, and trunc, instead of signextend, zeroextend,
and truncate, respectively, for consistency with the main IR.

llvm-svn: 70405

llvm-svn: 70391

llvm-svn: 70386

spillPhysRegAroundRegDefsUses() may have invalidated iterators stored in fixed_ IntervalPtrs. Reset them.

llvm-svn: 70378

llvm-svn: 70372

llvm-svn: 70366

anything larger than 64-bits, avoiding a crash.  This should
really be fixed to use APInts, though type legalization happens
to help us out and we get good code on the attached testcase at
least.

This fixes rdar://6836460

llvm-svn: 70360

llvm-svn: 70357

Determine allocation 'preference' with right register class. I haven't seen this changing codegen so no test case.

llvm-svn: 70351