llvm-svn: 85546

bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517

realignment regardless of whether it's strictly necessary.

llvm-svn: 85476

I'm going to redo this using the OptimizeForSize function attribute.

llvm-svn: 85426

opcode and operand with a tab.  Check for these instructions in the usual
places.

llvm-svn: 85411

llvm-svn: 85410

llvm-svn: 85406

llvm-svn: 85381

llvm-svn: 85379

In the new world order, BlockAddress can have a BasicBlock operand.
This doesn't permute much, because if you have a ConstantExpr (or
anything more specific than Constant) we still know the operand has
to be a Constant.

llvm-svn: 85375

llvm-svn: 85362

llvm-svn: 85361

eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen
change.

This unfortunately requires SystemZ to switch to the list-burr
scheduler, in order to handle the physreg defs properly, however
that's what LLVM has available at this time.

llvm-svn: 85357

llvm-svn: 85355

llvm-svn: 85351

use it to control tail merging when there is a tradeoff between performance
and code size.  When there is only 1 instruction in the common tail, we have
been merging.  That can be good for code size but is a definite loss for
performance.  Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3".  Radar 7338114.

Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level.  Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor.  If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.

llvm-svn: 85346

llvm-svn: 85341

llvm-svn: 85335

llvm-svn: 85334

default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.

llvm-svn: 85333

llvm-svn: 85332

llvm-svn: 85331

llvm-svn: 85329

llvm-svn: 85312

llvm-svn: 85311

llvm-svn: 85299

BL_pred and BLr9_pred.

llvm-svn: 85297

Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target.

llvm-svn: 85281

instruction format that already takes care of setting this.

llvm-svn: 85280

for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.

llvm-svn: 85271

llvm-svn: 85257

llvm-svn: 85255

llvm-svn: 85252

llvm-svn: 85235

llvm-svn: 85186

Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.

llvm-svn: 85184

llvm-svn: 85178

Remove LowerAllocations pass.
Update some more passes to treate free calls just like they were treating FreeInst.

llvm-svn: 85176

bits.  Johnny, please review -- I do not have a good track record of getting
these right.

llvm-svn: 85173

Patch by Johnny Chen.

llvm-svn: 85169