llvm-svn: 116083

llvm-svn: 116063

Small patch to restore home register stack space allocation for the Win64 case.  Add test case.  This code eventually needs to be tighter, since it's always allocating it, even in leaf routines.

llvm-svn: 116056

Canonicalize X86ISD::MOVDDUP nodes to v2f64 to make sure all cases match. Also eliminate unneeded isel patterns. rdar://8520311

llvm-svn: 115977

Patch by Cameron!

llvm-svn: 115480

The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.

Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics. 

MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces.  Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.

The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.

llvm-svn: 115243

llvm-svn: 114815

llvm-svn: 114811

llvm-svn: 114745

ARM cross-compiler on x86, because the MMO size did not match the type size.
This fixes the MMO size and also the size of the stack object to match the
type size.

llvm-svn: 114554

llvm-svn: 114529

llvm-svn: 114523

can access the stack due to how it is generated though.

llvm-svn: 114522

used with stack slots, but hey, lets be safe.

llvm-svn: 114521

llvm-svn: 114515

llvm-svn: 114508

the predicate to discover the number of sign bits.  Enhance X86's target lowering to provide
a useful response to this query.

llvm-svn: 114473

llvm-svn: 114463

(sbbl x, x) sets the registers to 0 or ~0.  Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.

This fixes <rdar://problem/8449754>.

llvm-svn: 114460

llvm-svn: 114453

llvm-svn: 114410

"getFixedStack" on the MachinePointerInfo class.  While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.

llvm-svn: 114406

of the getLoad methods.  This fixes at least one bug where an incorrect
svoffset is passed in (a potential combiner-aa miscompile).

llvm-svn: 114404

instead of srcvalue/offset pairs.  This corrects SV info for mem 
operations whose size is > 32-bits.

llvm-svn: 114401

llvm-svn: 114391

llvm-svn: 113766

llvm-svn: 113378

nodes to emit shuffles and don't do isel mask matching anymore.
- Add the selection of the remaining shuffle opcode (movddup)
- Introduce two new functions to "recognize" where we may get
potential folds and add several comments to them explaining why
they are not yet in the desidered shape.
- Add more patterns to fallback the case where we select
a specific shuffle opcode as if it could fold a load, but it
can't, so remap to a valid instruction.
- Add a couple of FIXMEs to address in the following days once
there's a good solution to the current folding problem.

llvm-svn: 113369

Factor out some x86 vector shuffle rewriting and add comments about the direction the shuffle lowering is heading to

llvm-svn: 113286

llvm-svn: 113267

llvm-svn: 113261

decouple MMX check from regular splat checks. Some refactoring is coming, and MMX should be left alone to be easily removed after moving to intrinsics

llvm-svn: 113247

llvm-svn: 113242

llvm-svn: 113239

llvm-svn: 113059

llvm-svn: 113058

llvm-svn: 113056

llvm-svn: 113055

llvm-svn: 113050

llvm-svn: 113048