llvm-svn: 7621

llvm-svn: 7620

llvm-svn: 7619

llvm-svn: 7618

llvm-svn: 7617

so get rid of the def/use parameters that were getting passed in.

**** This now changes the semantics of these methods to preserve the flags,
     not clobber them!

llvm-svn: 7602

llvm-svn: 7591

llvm-svn: 7588

llvm-svn: 7584

* Add a lot more DEBUG output, which is better structured than before
* Fix bug: Jello/2003-08-04-PhysRegLiveFailure.llx

llvm-svn: 7583

llvm-svn: 7534

llvm-svn: 7533

llvm-svn: 7531

llvm-svn: 7503

llvm-svn: 7497

TargetInstrInfo::ConvertConstantToIntType().

llvm-svn: 7390

   spilling values used by an instruction in the delay slot of the branch
   (which will eventually be moved before the branch).
2. Bug fix:  Delete the delay slot instr, not the branch instr, when
   moving delay slot instr. out!!!!
3. Move code to insert caller-saves moved here from SparcRegInfo:
   it is now machine-independent.

llvm-svn: 7389

llvm-svn: 7386

machine-independent.
Fix problem with using branch operand reg. as temp. reg. when
spilling values used by an instruction in the delay slot of the branch
(which will eventually be moved before the branch).

llvm-svn: 7385

llvm-svn: 7350

llvm-svn: 7349

llvm-svn: 7348

llvm-svn: 7347

llvm-svn: 7342

llvm-svn: 7341

    info (since multiple reg types may share the same reg class).
(2) Remove machine-specific regalloc. methods that are no longer needed.
    In particular, arguments and return value from a call do not need
    machine-specific code for allocation.
(3) Rename TargetRegInfo::getRegType variants to avoid unintentional
    overloading when an include file is omitted.

llvm-svn: 7329

found to consider regType info (since multiple reg types may share
the same reg class, e.g., single and double on Sparc).

llvm-svn: 7327

llvm-svn: 7250

llvm-svn: 7247

llvm-svn: 7246

llvm-svn: 7156

llvm-svn: 7155

which args can be substituted: defsOnly, defsAndUses or usesOnly.

llvm-svn: 7154

llvm-svn: 7153

(1) An int CC live range must be spilled if there are any interferences,
    even if no other "neighbour" in the interf. graph has been allocated
    that reg. yet.  This is actually true of any class with only one reg!

(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
    be spilled so that the machine-independent spill code doesn't have to
    make the machine-dependent decision of which CC name to use based on
    operand type: %xcc or %icc.  (These are two halves of the same
register.)

(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
    These should never have been the same, and this is necessary now for #2.

(4) All RDCCR and WRCCR instructions are directly generated with the
    phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
    deal with this.

llvm-svn: 7152

llvm-svn: 7112

llvm-svn: 7054

not just an Instruction*, at least in one unfortunate case:
the first operand to the va_arg instruction.
Modify ValueToDefVecMap to map from Value*, not Instruction*.

llvm-svn: 7052

system.

llvm-svn: 7014

llvm-svn: 6842