It is using a trivial rewriter that doesn't know how to insert spill code
requested by the standard spiller.

llvm-svn: 128688

The LocalStackSlotAllocation pass was creating illegal registers.

llvm-svn: 128687

llvm-svn: 128686

llvm-svn: 128683

llvm-svn: 128680

Thanks Eli!

llvm-svn: 128676

amounts to an UNDEFINED instruction.

llvm-svn: 128668

accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2

llvm-svn: 128665

Inst{4} = 0.

rdar://problem/9213022

llvm-svn: 128662

Add an extra run with -regalloc=basic to keep them honest.

llvm-svn: 128654

llvm-svn: 128650

isn't an exact float. Also "fpext float 1.0 to float" is invalid IR because
it's not performing an extension.

llvm-svn: 128647

Turn them into noop KILL instructions instead. This lets the scavenger know when
super-registers are killed and defined.

llvm-svn: 128645

A8.6.23 BLX (immediate)

rdar://problem/9212921

llvm-svn: 128644

llvm-svn: 128643

This way, shrinkToUses() will ignore the instruction that is about to be
deleted, and we avoid leaving invalid live ranges that SplitKit doesn't like.

Fix a misunderstanding in MachineVerifier about <def,undef> operands. The
<undef> flag is valid on def operands where it has the same meaning as <undef>
on a use operand. It only applies to sub-register defines which also read the
full register.

llvm-svn: 128642

llvm-svn: 128640

llvm-svn: 128639

llvm-svn: 128635

llvm-svn: 128634

llvm-svn: 128633

- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
  {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
  addrmode2.
- Add a new encoding bit to describe the index mode used and teach
  printAddrMode2Operand to check by the addressing mode which index
  mode to print.
- Testcases

llvm-svn: 128632

llvm-svn: 128631

llvm-svn: 128630

We don't expect the real "powf()" on some hosts (and powf() would be available on other hosts).
For consistency, std::pow(double,double) may be called instead.
Or, precision issue might attack us, to see unstable regalloc and stack coloring.

llvm-svn: 128629

Thanks Frits!

llvm-svn: 128628

llvm-svn: 128627

llvm-svn: 128626

InstCombine: Shrink "fcmp (fpext x), C" to "fcmp x, C" if C can be losslessly converted to the type of x.

Fixes PR9592.

llvm-svn: 128625

llvm-svn: 128624

llvm-svn: 128623

llvm-svn: 128622

llvm-svn: 128620

The rematerialized instruction may require a more constrained register class
than the register being spilled. In the test case, the spilled register has been
inflated to the DPR register class, but we are rematerializing a load of the
ssub_0 sub-register which only exists for DPR_VFP2 registers.

The register class is reinflated after spilling, so the conservative choice is
only temporary.

llvm-svn: 128610

This revision introduced a dependency cycle, as nlewycky mentioned by email.

llvm-svn: 128597

llvm-svn: 128594

llvm-svn: 128591

Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions.  With this fix, the entire test-suite passes with the Thumb integrated assembler.

llvm-svn: 128587

llvm-svn: 128586

  {STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser

llvm-svn: 128585