llvm-svn: 149146

llvm-svn: 149144

llvm-svn: 149118

we should (theoretically optimize and codegen ConstantDataVector as well
as ConstantVector.

llvm-svn: 149116

GEP instructions are there for the compiler and shouldn't really output much
code (if any at all). When a GEP is stored in the entry block, Fast ISel (for
one) will not know that it could fold it into further uses. For instance, inside
of the EH handling code. This results in a lot of unnecessary spills and loads
which bloat code and slows down pretty much everything.
<rdar://problem/10694814>

llvm-svn: 149114

llvm-svn: 149113

mid-level constant folding APIs instead of doing its own analysis.
This makes it more general (e.g. can now share a <2 x i64> with a
<4 x i32>) and avoid duplicating a bunch of logic.

llvm-svn: 149111

llvm-svn: 149097

we're at it, allow PatternMatch's "neg" pattern to match integer
vector negations, and enhance ComputeNumSigned bits to handle
shl of vectors.

llvm-svn: 149082

llvm-svn: 149078

llvm-svn: 149075

MachineBasicBlock::canFallThrough().  We're interested in the state of the
instruction (i.e., is this a barrier or not?), not if the instruction is
predicable or not.
rdar://10501092

llvm-svn: 149070

The live range of the source register may be extended when a redundant
copy is eliminated. Make sure any kill flags between the two copies are
cleared.

This fixes PR11765.

llvm-svn: 149069

Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors.

This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.

llvm-svn: 149057

more robust) ways to do what it was doing now.  Also, add static methods
for decoding a ShuffleVector mask.

llvm-svn: 149028

This boils down to using MachineOperand::readsReg() more.

This fixes PR11829 where a use ended up after the first def when
lowering REG_SEQUENCE instructions involving IMPLICIT_DEFs.

llvm-svn: 148996

and let linker handle the rest.

This finally fixes PR5329

llvm-svn: 148990

function. They don't appear to be used, and are inconsistent with handling of
other physreg intervals (i.e. intervals that are not live-in) where ranges are
not inserted for aliases.

llvm-svn: 148986

Always break upon finding a vreg operand (in Release as well as +Asserts). Remove assertion which can no longer trigger.

llvm-svn: 148984

llvm-svn: 148929

llvm-svn: 148897

A REG_SEQUENCE instruction is lowered into a sequence of partial defs:

  %vreg7:ssub_0<def,undef> = COPY %vreg20:ssub_0
  %vreg7:ssub_1<def> = COPY %vreg2
  %vreg7:ssub_2<def> = COPY %vreg2
  %vreg7:ssub_3<def> = COPY %vreg2

The first def needs an <undef> flag to indicate it is the beginning of
the live range, while the other defs are read-modify-write.  Previously,
we depended on LiveIntervalAnalysis to notice and fix the missing
<def,undef>, but that solution was never robust, it was causing problems
with ProcessImplicitDefs and the lowering of chained REG_SEQUENCE
instructions.

This fixes PR11841.

llvm-svn: 148879

llvm-svn: 148878

llvm-svn: 148825

llvm-svn: 148802

This change adds an new option --arm-enable-ehabi-descriptors that
enables emitting unwinding descriptors. This provides a mode with a
working backtrace() without the (currently broken) exception support.

llvm-svn: 148800

16 bits are sufficient to store attributes, tags and forms.

llvm-svn: 148799

Saves about 1.5% on debug info size.

rdar://10278198

llvm-svn: 148794

and clean up some other misc stuff.  Unlike ConstantArray, we will
prefer to emit .fill directives for "String" arrays that all have
the same value, since they are denser than emitting a .ascii

llvm-svn: 148793

This won't have an effect until EliminateRegSequences() starts setting
the undef flags.

llvm-svn: 148779

violation -- MC cannot depend on CodeGen.

Specifically, the MCTargetDesc component of each target is actually
a subcomponent of the MC library. As such, it cannot depend on the
target-independent code generator, because MC itself cannot depend on
the target-independent code generator. This change moved a flag from the
ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in
ARMException.cpp, leaving behind an 'extern' to refer back to it. That
layering order isn't viable givin the constraints outlined above.
Commandline flags are designed to be static specifically to avoid these
types of bugs.

Fixing this is likely going to require some non-trivial refactoring.

llvm-svn: 148759

llvm-svn: 148740

llvm-svn: 148725

This fixes a typo in r148589.

llvm-svn: 148724

llvm-svn: 148723

This change adds an new value to the --arm-enable-ehabi option that
disables emitting unwinding descriptors. This mode gives a working
backtrace() without the (currently broken) exception support.

llvm-svn: 148686

llvm-svn: 148662

llvm-svn: 148622

A register mask operand kills any live physreg that isn't preserved.
Unlike an implicit-def operand, the clobbered physregs are never live
afterwards.

This means LiveVariables has to track a much smaller number of live
physregs, and it should spend much less time in addRegisterDead().

llvm-svn: 148609

llvm-svn: 148594