llvm-svn: 129527

llvm-svn: 129012

Change the test to force a sign extension and expose the problem again.

llvm-svn: 129011

llvm-svn: 127786

but which is responsible for us doing really bad things to 256.bzip2.

llvm-svn: 126126

on Core 2 and Nehalem, so the code we generate is better than GCC's here.

llvm-svn: 126100

of a constant had a minor typo introduced when copying it from the book, which
caused it to favor negative approximations over positive approximations in many
cases. Positive approximations require fewer operations beyond the multiplication.

In the case of division by 3, we still generate code that is a single instruction
larger than GCC's code.

llvm-svn: 126097

llvm-svn: 126054

llvm-svn: 125832

llvm-svn: 122700

llvm-svn: 122560

llvm-svn: 122559

llvm-svn: 122495

  int test(unsigned long a, unsigned long b) { return -(a < b); }
compiles to
  _test:                              ## @test
    cmpq  %rsi, %rdi                  ## encoding: [0x48,0x39,0xf7]
    sbbl  %eax, %eax                  ## encoding: [0x19,0xc0]
    ret                               ## encoding: [0xc3]
instead of
  _test:                              ## @test
    xorl  %ecx, %ecx                  ## encoding: [0x31,0xc9]
    cmpq  %rsi, %rdi                  ## encoding: [0x48,0x39,0xf7]
    movl  $-1, %eax                   ## encoding: [0xb8,0xff,0xff,0xff,0xff]
    cmovael %ecx, %eax                ## encoding: [0x0f,0x43,0xc1]
    ret                               ## encoding: [0xc3]

llvm-svn: 122451

to catch cases where n != m with a shift.

llvm-svn: 121608

legalization time. Since at legalization time there is no mapping from
SDNode back to the corresponding LLVM instruction and the return
SDNode is target specific, this requires a target hook to check for
eligibility. Only x86 and ARM support this form of sibcall optimization
right now.
rdar://8707777

llvm-svn: 120501

llvm-svn: 119947

there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.

This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.

llvm-svn: 112861

llvm-svn: 112411

for lowering without sse2.  Add a couple of new testcases.

Fixes a few libgomp tests and latent bugs.  Remove a few todos.

llvm-svn: 109078

llvm-svn: 105375

llvm-svn: 97450

code with lots of bitfields.

llvm-svn: 95809

llvm-svn: 93373

llvm-svn: 93372

llvm-svn: 92511

llvm-svn: 91823

llvm-svn: 85334

llvm-svn: 85332

llvm-svn: 85331

llvm-svn: 85329

llvm-svn: 77584

llvm-svn: 74509

llvm-svn: 74508

llvm-svn: 73472

llvm-svn: 73471

add a few suggestions from looking at some assembly code.

llvm-svn: 73210

even on Core2, not just AMD processors which was a surprise to me.

llvm-svn: 72396

llvm-svn: 72387

related transformations out of target-specific dag combine into the
ARM backend.  These were added by Evan in r37685 with no testcases
and only seems to help ARM (e.g. test/CodeGen/ARM/select_xform.ll).

Add some simple X86-specific (for now) DAG combines that turn things
like cond ? 8 : 0  -> (zext(cond) << 3).  This happens frequently
with the recently added cp constant select optimization, but is a
very general xform.  For example, we now compile the second example
in const-select.ll to:

_test:
        movsd   LCPI2_0, %xmm0
        ucomisd 8(%esp), %xmm0
        seta    %al
        movzbl  %al, %eax
        movl    4(%esp), %ecx
        movsbl  (%ecx,%eax,4), %eax
        ret

instead of:

_test:
        movl    4(%esp), %eax
        leal    4(%eax), %ecx
        movsd   LCPI2_0, %xmm0
        ucomisd 8(%esp), %xmm0
        cmovbe  %eax, %ecx
        movsbl  (%ecx), %eax
        ret

This passes multisource and dejagnu.

llvm-svn: 66779