When an instruction as written requires 32-bit mode and we're assembling
in 64-bit mode, or vice-versa, issue a more specific diagnostic about
what's wrong.

rdar://12700702

llvm-svn: 167937

llvm-svn: 167922

llvm-svn: 167916

Set FFLOOR for vectors to expand on CellSPU to keep instruction selection from failing on llvm.floor of a vector.

llvm-svn: 167914

Do some cleanup of the code while here.

Inspired by patch by Logan Chien!

llvm-svn: 167904

generate them from PPCELFObjectWriter::getRelocTypeInner
as appropriate.

llvm-svn: 167864

 - lwaux
 - lhzux
 - stbu

llvm-svn: 167863

operand field name mismatches in:
 - AForm_3  (fmul, fmuls)
 - XFXForm_5 (mtcrf)
 - XFLForm (mtfsf)

llvm-svn: 167862

by using a new instruction format BForm_1.

llvm-svn: 167861

using a new instruction format AForm_4.

llvm-svn: 167860

chain is correctly setup.

As an example, if the original load must happen before later stores, we need
to make sure the constructed VZEXT_LOAD is constrained to be before the stores.

rdar://12684358

llvm-svn: 167859

This allows me to begin enabling (or backing out) misched by default
for one subtarget at a time. To run misched we typically want to:
- Disable SelectionDAG scheduling (use the source order scheduler)
- Enable more aggressive coalescing (until we decide to always run the coalescer this way)
- Enable MachineScheduler pass itself.

Disabling PostRA sched may follow for some subtargets.

llvm-svn: 167826

Add a blank line.

llvm-svn: 167819

This infrastructure is generally useful for any target that wants to
strongly prefer two instructions to be adjacent after scheduling.

A following checkin will add target-specific hooks with unit
tests. Then this feature will be enabled by default with misched.

llvm-svn: 167742

llvm-svn: 167737

llvm-svn: 167719

- Fix operand order for atomic sub, where the minuend is the value
  loaded from memory and the subtrahend is the parameter specified.

llvm-svn: 167718

Each SM and PTX version is modeled as a subtarget feature/CPU. Additionally,
PTX 3.1 is added as the default PTX version to be out-of-the-box compatible
with CUDA 5.0.

Available CPUs for this target:

  sm_10 - Select the sm_10 processor.
  sm_11 - Select the sm_11 processor.
  sm_12 - Select the sm_12 processor.
  sm_13 - Select the sm_13 processor.
  sm_20 - Select the sm_20 processor.
  sm_21 - Select the sm_21 processor.
  sm_30 - Select the sm_30 processor.
  sm_35 - Select the sm_35 processor.

Available features for this target:

  ptx30 - Use PTX version 3.0.
  ptx31 - Use PTX version 3.1.
  sm_10 - Target SM 1.0.
  sm_11 - Target SM 1.1.
  sm_12 - Target SM 1.2.
  sm_13 - Target SM 1.3.
  sm_20 - Target SM 2.0.
  sm_21 - Target SM 2.1.
  sm_30 - Target SM 3.0.
  sm_35 - Target SM 3.5.

llvm-svn: 167699

llvm-svn: 167696

llvm-svn: 167685

llvm-svn: 167673

llvm-svn: 167671

llvm-svn: 167670

llvm-svn: 167669

In the process of migrating optimizations from the simplify-libcalls pass
to the instcombine pass I noticed that a few functions are missing from
the target library information.  These functions need to be available for
querying in the instcombine library call simplifiers.  More functions will
probably be added in the future as more simplifiers are migrated to
instcombine.

llvm-svn: 167659

mov lr, pc
b.w _foo

The "mov" instruction doesn't set bit zero to one, it's putting incorrect
value in lr. It messes up backtraces.

rdar://12663632

llvm-svn: 167657

llvm-svn: 167652

Affects SM 2.0+.  Fixes bug 13324.

llvm-svn: 167646

Based on the patch by Logan Chien!

llvm-svn: 167633

reverts r126226.

llvm-svn: 167632

llvm-svn: 167622

rdar://12340498

llvm-svn: 167620

llvm-svn: 167607

Improve ARM build attribute emission for architectures types.
This also changes the default architecture emitted for a generic CPU to "v7".

llvm-svn: 167574

- Add RTM code generation support throught 3 X86 intrinsics:
  xbegin()/xend() to start/end a transaction region, and xabort() to abort a
  tranaction region

llvm-svn: 167573

Patch by Sasa Stankovic.

llvm-svn: 167548

llvm-svn: 167546

llvm-svn: 167545

This also changes the default architecture emitted for a generic CPU to "v7".

llvm-svn: 167540

classes.  For my test case the number of errors drop from 356 to 21.
Part of rdar://12594152

llvm-svn: 167508