llvm-svn: 140705

llvm-svn: 140704

llvm-svn: 140703

Get rid of some of the no-longer-needed parts of PTXAsmPrinter.

llvm-svn: 140698

Lay some groundwork for converting to MC-based asm printer. This is the first
of probably many patches to bring the back-end back up-to-date with all of the
recent MC changes.

llvm-svn: 140697

Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.

llvm-svn: 140696

llvm-svn: 140680

The copies caused use-after-free bugs on std::string implementations without COW (i.e. anything but libstdc++)

llvm-svn: 140679

I'll clean up the source in the next commit.

llvm-svn: 140663

llvm-svn: 140661

This also enables domain swizzling for AVX code which required a few
trivial test changes.

The pass will be moved to lib/CodeGen shortly.

llvm-svn: 140659

llvm-svn: 140655

llvm-svn: 140653

I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass.  They are essentially doing the same
thing.

llvm-svn: 140652

Add inst alias to handle these assembly forms. Add tests, too.

rdar://10178799

llvm-svn: 140647

current IR-level pass.

The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).

Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.

llvm-svn: 140646

of the instruction definitions using Pat<>.

llvm-svn: 140644

Naming conventions consistency. No functional change.

llvm-svn: 140636

llvm-svn: 140624

a couple of outstanding issues with frame objects occuring as instruction
operands.

llvm-svn: 140616

llvm-svn: 140615

Return numbers of 64-bit registers.

llvm-svn: 140609

llvm-svn: 140607

llvm-svn: 140598

llvm-svn: 140593

llvm-svn: 140581

llvm-svn: 140570

llvm-svn: 140569

registers, so there is no need to check here.

llvm-svn: 140568

llvm-svn: 140560

llvm-svn: 140556

llvm-svn: 140549

llvm-svn: 140548

printing of local offsets

llvm-svn: 140547

llvm-svn: 140536

llvm-svn: 140535

llvm-svn: 140534

llvm-svn: 140533

llvm-svn: 140532

PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval

llvm-svn: 140516