an argument to every operand printing function.  Requires some slight
tweaks to x86, the only user.

llvm-svn: 24541

llvm-svn: 24538

llvm-svn: 24536

llvm-svn: 24535

changes allow us to generate the following code:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vaddfp v0, v0, v0
        stvx v0, r2, r3
        blr

for this llvm:

void %foo(<4 x float>* %a) {
entry:
        %tmp1 = load <4 x float>* %a
        %tmp2 = add <4 x float> %tmp1, %tmp1
        store <4 x float> %tmp2, <4 x float>* %a
        ret void
}

llvm-svn: 24534

Getting in on the custom lowering thing, yay
evilness with fp setcc, yuck
trivial int select, hmmm
in memory args for functions, yay
DIV and REM, always handy.  They should be custom lowered though.

Lots more stuff compiles now (go go single source!).  Of course, none of it
probably works, but that is what the nightly tester can find out :)

llvm-svn: 24533

llvm-svn: 24526

llvm-svn: 24525

llvm-svn: 24522

that we can use the correct SPR numbers in the InstrInfo.td file.  This is
necessary to support VRsave.

llvm-svn: 24521

llvm-svn: 24520

llvm-svn: 24517

enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.

llvm-svn: 24516

llvm-svn: 24513

and make a few changes to the legalization machinery to support more than
16 types.

llvm-svn: 24511

createPPCPatternInstructionSelector -> createPPCISelPattern

llvm-svn: 24510

llvm-svn: 24505

this to be something sane, but in the mean time it is unused, so safe to
make something bogus.

llvm-svn: 24504

llvm-svn: 24503

llvm-svn: 24501

llvm-svn: 24495

llvm-svn: 24492

next up: support argument passing in memory, not just registers

llvm-svn: 24490

Registers.  Apologies to Jim if the scheduling info so far isn't accurate.

There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.

llvm-svn: 24489

llvm-svn: 24486

llvm-svn: 24485

llvm-svn: 24483

generates it.  Make MVT::Vector expand-only, and remove the code in
Legalize that attempts to legalize it.

The plan for supporting N x Type is to continually epxand it in ExpandOp
until it gets down to 2 x Type, where it will be scalarized into a pair of
scalars.

llvm-svn: 24482

llvm-svn: 24481

llvm-svn: 24479

based on TargetType.

llvm-svn: 24478

llvm-svn: 24477

or native Win32

llvm-svn: 24476

conditionals.

llvm-svn: 24475

llvm-svn: 24473

llvm-svn: 24472

file.

llvm-svn: 24470

llvm-svn: 24469

llvm-svn: 24468

CPI ids

llvm-svn: 24467