llvm-svn: 118999

llvm-svn: 118998

- Get the opcode once.
- Add a ParserMatchClass to reglist.

llvm-svn: 118997

future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.

llvm-svn: 118995

 - What was I thinking?????

llvm-svn: 118992

llvm-svn: 118987

llvm-svn: 118985

2. Fixing several errors in disassembler uncovered by test cases.
3. Fixing invalid encoding of PCMPEQ and PCMPNE uncovered by test cases.

llvm-svn: 118969

llvm-svn: 118968

llvm-svn: 118965

instructions.

llvm-svn: 118963

flag for the LDRT/STRT family instructions as a side effect.

llvm-svn: 118955

llvm-svn: 118954

llvm-svn: 118951

2. Fixing improper immediate mode reverse subtract.

llvm-svn: 118948

llvm-svn: 118946

llvm-svn: 118945

llvm-svn: 118943

llvm-svn: 118942

2. Parsing .word directive in MBlaze asm parser
3. Fixing hack where memory instructions reversed order of last two parameters
4. Fixing many improperly encoded instructions
5. Support parsing special instructions (MFS,MTS,etc.)
6. Removing unused functions from inst printer

llvm-svn: 118941

llvm-svn: 118939

Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.

llvm-svn: 118938

an address is in a different block, get it into a register and go
from there.

llvm-svn: 118936

llvm-svn: 118935

llvm-svn: 118926

to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.

llvm-svn: 118925

llvm-svn: 118924

Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.

llvm-svn: 118922

llvm-svn: 118921

llvm-svn: 118919

from the user of the address, fall back to just using the
address in a register instead of bailing out of fast-isel
altogether.

llvm-svn: 118917

llvm-svn: 118916

llvm-svn: 118907

llvm-svn: 118905

llvm-svn: 118903

llvm-svn: 118896

support for the case where alignment<value size.

These cases were silently miscompiled before this patch.
Now they are overly verbose -especially storing is- and
any front-end should still avoid misaligned memory 
accesses as much as possible. The bit juggling algorithm
added here probably has some room for improvement still.

llvm-svn: 118889

missed. Update some comments accordingly.

Fixes rdar://8652289

llvm-svn: 118888

llvm-svn: 118865

llvm-svn: 118864