llvm-svn: 118999

llvm-svn: 118998

- Get the opcode once.
- Add a ParserMatchClass to reglist.

llvm-svn: 118997

future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.

llvm-svn: 118995

 - What was I thinking?????

llvm-svn: 118992

llvm-svn: 118985

llvm-svn: 118968

llvm-svn: 118965

instructions.

llvm-svn: 118963

flag for the LDRT/STRT family instructions as a side effect.

llvm-svn: 118955

llvm-svn: 118951

llvm-svn: 118946

llvm-svn: 118945

llvm-svn: 118942

llvm-svn: 118939

Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.

llvm-svn: 118938

an address is in a different block, get it into a register and go
from there.

llvm-svn: 118936

llvm-svn: 118935

llvm-svn: 118926

to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.

llvm-svn: 118925

llvm-svn: 118924

Add some missing isel predicates on def : pat patterns to avoid generating VFP vmla / vmls (they cause stalls). Disabling them in isel is properly not a right solution, I'll look into a proper solution next.

llvm-svn: 118922

llvm-svn: 118921

llvm-svn: 118919

llvm-svn: 118907

llvm-svn: 118905

missed. Update some comments accordingly.

Fixes rdar://8652289

llvm-svn: 118888

llvm-svn: 118859

llvm-svn: 118854

llvm-svn: 118843

llvm-svn: 118835

llvm-svn: 118829

llvm-svn: 118827

llvm-svn: 118823

Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
More tests to come.

llvm-svn: 118819

instructions.

llvm-svn: 118801

llvm-svn: 118794

llvm-svn: 118767

llvm-svn: 118761

llvm-svn: 118757