the max itself, so it is not easy to write a test case for this, but I added a
test case that would fail if the code in AsmPrinter were removed.

llvm-svn: 129432

llvm-svn: 129429

alignment for its type, use the minimum of the specified alignment and the ABI
alignment. This fixes <rdar://problem/9275290>.

llvm-svn: 129428

llvm-svn: 129419

rdar://problem/9273947

llvm-svn: 129411

The ARMARM specifies these instructions as unpredictable when storing the
writeback register. This shouldn't affect code generation much since storing a
pointer to itself is quite rare.

llvm-svn: 129409

llvm-svn: 129403

Now that we have a first-class way to represent unaligned loads, the unaligned
load intrinsics are superfluous.

First part of <rdar://problem/8460511>.

llvm-svn: 129401

In addition, the base register is not rGPR, but GPR with th exception that:

    if n == 15 then UNPREDICTABLE

rdar://problem/9273836

llvm-svn: 129391

rdar://problem/9269047

llvm-svn: 129387

be specified as '1' (add = TRUE).

Also add a utility function for Thumb2.

llvm-svn: 129377

llvm-svn: 129365

stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.

llvm-svn: 129345

Encoding T1 (tBcc)
if cond == '1110' then UNDEFINED;

rdar://problem/9268681

llvm-svn: 129325

rdar://problem/9267838

llvm-svn: 129320

llvm-svn: 129313

llvm-svn: 129311

This fixes http://llvm.org/bugs/show_bug.cgi?id=9653

llvm-svn: 129303

Fix the bug where the immediate shift amount for Thumb logical shift instructions are incorrectly disassembled.

rdar://problem/9266265

llvm-svn: 129298

Fix another using-CPSR-twice bug in my ADCS/SBCS cleanups, and make proper use of the Commutable bit.

llvm-svn: 129294

llvm-svn: 129288

invalid instructions.

llvm-svn: 129286

disassembler API.  Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
  blx _puts
instead of this:
  blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
  movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 129284

llvm-svn: 129271

llvm-svn: 129248

InstAlias doesn't allow matching immediate operands, so we have to write
C++ code to do this.

llvm-svn: 129223

llvm-svn: 129160

Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time.

llvm-svn: 129152

llvm-svn: 129148

PR9650
rdar://problem/9257565

llvm-svn: 129147

PR9648
rdar://problem/9257634

llvm-svn: 129146

The previous cleanup of LDRD got overzealous and removed it, causing post-RA
scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued.

rdar://9244161

llvm-svn: 129144

Add more test cases to exercise the logical branches related to the above change.

llvm-svn: 129117

with the newer, cleaner model. It uses the IAPrinter class to hold the
information that is needed to match an instruction with its alias. This also
takes into account the available features of the platform.

There is one bit of ugliness. The way the logic determines if a pattern is
unique is O(N**2), which is gross. But in reality, the number of items it's
checking against isn't large. So while it's N**2, it shouldn't be a massive time
sink.

llvm-svn: 129110

llvm-svn: 129107

llvm-svn: 129105

llvm-svn: 129104

llvm-svn: 129101

llvm-svn: 129099

Add some test cases.

llvm-svn: 129098