- Jan 19, 2012
-
-
Evan Cheng authored
llvm-svn: 148462
-
Evan Cheng authored
to instruction right after the last instruction in the bundle. - Add a finalizeBundle() variant that doesn't specify LastMI. Instead, the code will find the last instruction in the bundle by following the 'InsideBundle' marker. This is useful in case bundles are formed early (i.e. during MI scheduling) but finalized later (i.e. after register allocator has finished rewriting virtual registers with physical registers). llvm-svn: 148444
-
Evan Cheng authored
llvm-svn: 148440
-
Jakob Stoklund Olesen authored
This SelectionDAG node will be attached to call nodes by LowerCall(), and eventually becomes a MO_RegisterMask MachineOperand on the MachineInstr representing the call instruction. LowerCall() will attach a register mask that depends on the calling convention. llvm-svn: 148436
-
- Jan 18, 2012
-
-
Lang Hames authored
llvm-svn: 148408
-
Nadav Rotem authored
Fix a bug in the type-legalization of vector integers. When we bitcast one vector type to another, we must not bitcast the result if one type is widened while the other is promoted. llvm-svn: 148383
-
Pete Cooper authored
Fix ISD::REG_SEQUENCE to accept physical registers and change TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE llvm-svn: 148377
-
- Jan 17, 2012
-
-
Nadav Rotem authored
llvm-svn: 148337
-
Craig Topper authored
llvm-svn: 148297
-
Andrew Trick authored
llvm-svn: 148291
-
Andrew Trick authored
Responding to code review. llvm-svn: 148290
-
Andrew Trick authored
More short term hackery until we have a way to configure passes that work on LiveIntervals. llvm-svn: 148289
-
Rafael Espindola authored
or clang bootstrap. I will keep an eye on the bots. Original message: Only emit the Leh_func_endN symbol when needed. llvm-svn: 148283
-
Pete Cooper authored
Changed flag operand of ISD::FP_ROUND to TargetConstant as it should not get checked for legalisation llvm-svn: 148275
-
Lang Hames authored
llvm-svn: 148268
-
David Blaikie authored
Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly. (This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them) llvm-svn: 148262
-
- Jan 16, 2012
-
-
Hal Finkel authored
AggressiveAntiDepBreaker needs to skip debug values because a debug value does not have a corresponding SUnit llvm-svn: 148260
-
Jakob Stoklund Olesen authored
It is safe to move uses of such registers. llvm-svn: 148259
-
Jakob Stoklund Olesen authored
llvm-svn: 148251
-
Jakob Stoklund Olesen authored
Register masks will be used as a compact representation of large clobber lists. Currently, an x86 call instruction has some 40 operands representing call-clobbered registers. That's more than 1kB of useless operands per call site. A register mask operand references a bit mask of call-preserved registers, everything else is clobbered. The bit mask will typically come from TargetRegisterInfo::getCallPreservedMask(). By abandoning ImplicitDefs for call-clobbered registers, it also becomes possible to share call instruction descriptions between calling conventions, and we can get rid of the WINCALL* instructions. This patch introduces the new operand kind. Future patches will add RegMask support to target-independent passes before finally the fixed clobber lists can be removed from call instruction descriptions. llvm-svn: 148250
-
David Blaikie authored
llvm-svn: 148230
-
Pete Cooper authored
Changed intrinsic ID operand to a target constant as its not used in any arithmetic so should not be checked in legalisation llvm-svn: 148228
-
- Jan 15, 2012
-
-
Nadav Rotem authored
We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. llvm-svn: 148225
-
Benjamin Kramer authored
llvm-svn: 148218
-
Benjamin Kramer authored
llvm-svn: 148217
-
Craig Topper authored
llvm-svn: 148205
-
- Jan 14, 2012
-
-
Duncan Sands authored
non-determinism in the 32 bit dragonegg buildbot. Original commit message: Only emit the Leh_func_endN symbol when needed. llvm-svn: 148191
-
Rafael Espindola authored
llvm-svn: 148175
-
Andrew Trick authored
llvm-svn: 148174
-
Andrew Trick authored
llvm-svn: 148173
-
Andrew Trick authored
llvm-svn: 148172
-
Andrew Trick authored
llvm-svn: 148171
-
Andrew Trick authored
llvm-svn: 148170
-
Evan Cheng authored
live across BBs before register allocation. This miscompiled 197.parser when a cmp + b are optimized to a cbnz instruction even though the CPSR def is live-in a successor. cbnz r6, LBB89_12 ... LBB89_12: ble LBB89_1 The fix consists of two parts. 1) Teach LiveVariables that some unallocatable registers might be liveouts so don't mark their last use as kill if they are. 2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional branch does not kill CPSR. rdar://10676853 llvm-svn: 148168
-
Rafael Espindola authored
llvm-svn: 148156
-
- Jan 13, 2012
-
-
Rafael Espindola authored
llvm-svn: 148150
-
Andrew Trick authored
llvm-svn: 148143
-
Andrew Trick authored
llvm-svn: 148105
-
Andrew Trick authored
llvm-svn: 148103
-
Andrew Trick authored
llvm-svn: 148102
-