llvm-svn: 27885

llvm-svn: 27881

can be converted to losslessly, we can continue the conversion to a direct call.

llvm-svn: 27880

to a vector shuffle.
- VECTOR_SHUFFLE lowering change in preparation for more efficient codegen
of vector shuffle with zero (or any splat) vector.

llvm-svn: 27875

DAG combiner can turn a VAND V, <-1, 0, -1, -1>, i.e. vector clear elements,
into a vector shuffle with a zero vector. It only does so when TLI tells it
the xform is profitable.

llvm-svn: 27874

CodeGen/PowerPC/2006-04-19-vmaddfp-crash.ll

llvm-svn: 27868

llvm-svn: 27863

but i64 is not. If possible, change a i64 op to a f64 (e.g. load, constant)
and then cast it back.

llvm-svn: 27849

llvm-svn: 27847

llvm-svn: 27846

  instructions.
- Fixed a commute vector_shuff bug.

llvm-svn: 27845

llvm-svn: 27844

llvm-svn: 27843

- Added more movhlps and movlhps patterns.

llvm-svn: 27842

llvm-svn: 27840

llvm-svn: 27836

- Increase cost (complexity) of patterns which match mov{h|l}ps ops. These
  are preferred over shufps in most cases.

llvm-svn: 27835

llvm-svn: 27834

llvm-svn: 27832

llvm-svn: 27831

llvm-svn: 27830

llvm-svn: 27829

llvm-svn: 27828

llvm-svn: 27827

llvm-svn: 27821

llvm-svn: 27819

- PINSRWrmi encoding bug.

llvm-svn: 27818

llvm-svn: 27817

llvm-svn: 27816

llvm-svn: 27815

llvm-svn: 27814

llvm-svn: 27813

llvm-svn: 27812

llvm-svn: 27811

llvm-svn: 27810

llvm-svn: 27809

void foo2(vector float *A, vector float *B) {
  vector float C = (vector float)vec_cmpeq(*A, *B);
  if (!vec_any_eq(*A, *B))
    *B = (vector float){0,0,0,0};
  *A = C;
}

llvm-svn: 27808

llvm-svn: 27807

llvm-svn: 27806

If an altivec predicate compare is used immediately by a branch, don't
use a (serializing) MFCR instruction to read the CR6 register, which requires
a compare to get it back to CR's.  Instead, just branch on CR6 directly. :)

For example, for:
void foo2(vector float *A, vector float *B) {
  if (!vec_any_eq(*A, *B))
    *B = (vector float){0,0,0,0};
}

We now generate:

_foo2:
        mfspr r2, 256
        oris r5, r2, 12288
        mtspr 256, r5
        lvx v2, 0, r4
        lvx v3, 0, r3
        vcmpeqfp. v2, v3, v2
        bne cr6, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
        vxor v2, v2, v2
        stvx v2, 0, r4
        mtspr 256, r2
        blr
LBB1_2: ; UnifiedReturnBlock
        mtspr 256, r2
        blr

instead of:

_foo2:
        mfspr r2, 256
        oris r5, r2, 12288
        mtspr 256, r5
        lvx v2, 0, r4
        lvx v3, 0, r3
        vcmpeqfp. v2, v3, v2
        mfcr r3, 2
        rlwinm r3, r3, 27, 31, 31
        cmpwi cr0, r3, 0
        beq cr0, LBB1_2 ; UnifiedReturnBlock
LBB1_1: ; cond_true
        vxor v2, v2, v2
        stvx v2, 0, r4
        mtspr 256, r2
        blr
LBB1_2: ; UnifiedReturnBlock
        mtspr 256, r2
        blr

This implements CodeGen/PowerPC/vec_br_cmp.ll.

llvm-svn: 27804