- Add RTM code generation support throught 3 X86 intrinsics:
  xbegin()/xend() to start/end a transaction region, and xabort() to abort a
  tranaction region

llvm-svn: 167573

This patch migrates the strspn optimizations from the simplify-libcalls
pass into the instcombine library call simplifier.

llvm-svn: 167568

values in a map that can be passed to consumers. Add a testcase that
ensures this works for llvm-dwarfdump.

llvm-svn: 167558

is available.

llvm-svn: 167552

Patch by Sasa Stankovic.

llvm-svn: 167548

llvm-svn: 167546

llvm-svn: 167545

This also changes the default architecture emitted for a generic CPU to "v7".

llvm-svn: 167540

[asan] fix bug 14277 (asan needs to fail with fata error if an __asan interface function is being redefined. Before this fix asan asserts)

llvm-svn: 167529

misched is disabled by default. With -enable-misched, these heuristics
balance the schedule to simultaneously avoid saturating processor
resources, expose ILP, and minimize register pressure. I've been
analyzing the performance of these heuristics on everything in the
llvm test suite in addition to a few other benchmarks. I would like
each heuristic check to be verified by a unit test, but I'm still
trying to figure out the best way to do that. The heuristics are still
in considerable flux, but as they are refined we should be rigorous
about unit testing the improvements.

llvm-svn: 167527

instructions without relying on liveintervals.

llvm-svn: 167526

llvm-svn: 167525

updating an abstract DIE or not. If we are, then we use that. Its children will
be added on later, as well as the object pointer attribute. Otherwise, this
function may be called with a concrete DIE twice and adding the children and
object pointer attribute to it twice.
<rdar://problem/12401423&12600340>

llvm-svn: 167524

classes.  For my test case the number of errors drop from 356 to 21.
Part of rdar://12594152

llvm-svn: 167508

llvm-svn: 167505

llvm-svn: 167501

registers.  Previously, the register we being marked as implicitly defined, but
not killed.  In some cases this would cause the register scavenger to spill a
dead register.

Also, use an empty register mask to simplify the logic and to reduce the memory
footprint.
rdar://12592448

llvm-svn: 167499

register masks.  This is an obvious and necessary fix for a soon to be committed
patch.  No test case possible at this time.  Reviewed by Jakob.

llvm-svn: 167498

llvm-svn: 167488

llvm-svn: 167480

llvm-svn: 167477

This patch adds the interface to expose events from MCJIT when an object is emitted or freed and implements the MCJIT functionality to send those events.  The IntelJITEventListener implementation is left empty for now.  It will be fleshed out in a future patch.

llvm-svn: 167475

llvm-svn: 167467

llvm-svn: 167445

Expose the processor resources defined by the machine model to the
scheduler and other clients through the TargetSchedule interface.

Normalize each resource count with respect to other kinds of
resources. This allows scheduling heuristics to balance resources
against other kinds of resources and latency.

llvm-svn: 167444

llvm-svn: 167443

This is in preparation for adding "weak" DAG edges, but generally
simplifies the design.

llvm-svn: 167435

llvm-svn: 167422

llvm-svn: 167421

llvm-svn: 167412

llvm-svn: 167410

possible buffer change with a .macro directive.

rdar://12637628

llvm-svn: 167408

 - We only support this when the client didn't claim to know the file size.

llvm-svn: 167407

llvm-svn: 167402

llvm-svn: 167401

Prior to this patch RuntimeDyld attempted to re-apply relocations every time reassignSectionAddress was called (via MCJIT::mapSectionAddress).  In addition to being inefficient and redundant, this led to a problem when a section was temporarily moved too far away from another section with a relative relocation referencing the section being moved.  To fix this, I'm adding a new method (finalizeObject) which the client can call to indicate that it is finished rearranging section addresses so the relocations can safely be applied.

llvm-svn: 167400

to be extended to a full register.   This is modeled in the IR by marking
the return value (or argument) with a signext or zeroext attribute.

However, while these attributes are respected for function arguments,
they are currently ignored for function return values by the PowerPC
back-end.  This patch updates PPCCallingConv.td to ask for the promotion
to i64, and fixes LowerReturn and LowerCallResult to implement it.

The new test case verifies that both arguments and return values are
properly extended when passing them; and also that the optimizers
understand incoming argument and return values are in fact guaranteed
by the ABI to be extended.

The patch caused a spurious breakage in CodeGen/PowerPC/coalesce-ext.ll,
since the test case used a "ret" instruction to create a use of an i32
value at the end of the function (to set up data flow as required for
what the test is intended to test).  Since there's now an implicit
promotion to i64, that data flow no longer works as expected.  To fix
this, this patch now adds an extra "add" to ensure we have an appropriate
use of the i32 value.

llvm-svn: 167396

llvm-svn: 167395

The Z constraint specifies an r+r memory address, and the y modifier expands
to the "r, r" in the asm string. For this initial implementation, the base
register is forced to r0 (which has the special meaning of 0 for r+r addressing
on PowerPC) and the full address is taken in the second register. In the
future, this should be improved.

llvm-svn: 167388

This patch expands the SEXTLOAD, ZEXTLOAD, and EXTLOAD operations for
vector types when altivec is enabled.

llvm-svn: 167386