SSE2, however it's possible to disable SSE2, and the subtarget support
code thinks that if 64-bit implies SSE2 and SSE2 is disabled then
64-bit should also be disabled. Instead, just mark all the 64-bit
subtargets as explicitly supporting SSE2.

Also, move the code that makes -march=x86-64 enable 64-bit support by
default to only apply when there is no explicit subtarget. If you
need to specify a subtarget and you want 64-bit code, you'll need to
select a subtarget that supports 64-bit code.

llvm-svn: 63575

llvm-svn: 63574

except LegalizeOp itself.

llvm-svn: 63560

option to make the -fno- form on the option.  We also document the new
form in the CommandLine documentation.

llvm-svn: 63559

Live interval reconstruction needs to account for this, and scour its maps to
prevent dangling references.

llvm-svn: 63558

among others.

llvm-svn: 63555

Add an assert to check HasX86_64 status.

llvm-svn: 63552

llvm-svn: 63545

llvm-svn: 63544

llvm-svn: 63543

llvm-svn: 63542

llvm-svn: 63540

llvm-svn: 63537

llvm-svn: 63536

tests.  Thanks for the beautiful reduced testcase Duncan!

llvm-svn: 63529

llvm-svn: 63527

llvm-svn: 63523

Made the common case of default address space directive as non-virtual for performance reasons. Provide a single virtual interface for directives of all sizes in  non-default address spaces.

llvm-svn: 63521

and remove trailing whitespace.  No functionality
change.

llvm-svn: 63511

llvm-svn: 63510

llvm-svn: 63509

llvm-svn: 63506

Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the condition. It's normally transformed by the dag combiner, unless the condition is set by a arithmetic op with overflow.

llvm-svn: 63505

llvm-svn: 63504

llvm-svn: 63501

llvm-svn: 63500

llvm-svn: 63498

var-args, and don't allow FP return values

llvm-svn: 63495

crashes or wrong code with codegen of large integers:
eliminate the legacy getIntegerVTBitMask and
getIntegerVTSignBit methods, which returned their
value as a uint64_t, so couldn't handle huge types.

llvm-svn: 63494

llvm-svn: 63493

llvm-svn: 63492

Fix an issue in PHI construction that was exposed by GCC 4.2 producing a different set iteration order for the reg_iterator.

llvm-svn: 63490

llvm-svn: 63489

llvm-svn: 63488

turn icmp eq a+x, b+x into icmp eq a, b if a+x or b+x has other uses. This
may have been increasing register pressure leading to the bzip2 slowdown.

llvm-svn: 63487

llvm-svn: 63486

llvm-svn: 63485

improvements to the EvaluateInDifferentType code.  This code works 
by just inserted a bunch of new code and then seeing if it is 
useful.  Instcombine is not allowed to do this: it can only insert
new code if it is useful, and only when it is converging to a more
canonical fixed point.  Now that we iterate when DCE makes progress,
this causes an infinite loop when the code ends up not being used.

llvm-svn: 63483

returned by getShiftAmountTy may be too small
to hold shift values (it is an i8 on x86-32).
Before and during type legalization, use a large
but legal type for shift amounts: getPointerTy;
afterwards use getShiftAmountTy, fixing up any
shift amounts with a big type during operation
legalization.  Thanks to Dan for writing the
original patch (which I shamelessly pillaged).

llvm-svn: 63482

simplifydemandedbits to simplify instructions with *multiple
uses* in contexts where it can get away with it.  This allows
it to simplify the code in multi-use-or.ll into a single 'add 
double'.

This change is particularly interesting because it will cover
up for some common codegen bugs with large integers created due
to the recent SROA patch.  When working on fixing those bugs,
this should be disabled.

llvm-svn: 63481