increase in the debug line info section, and it's causing
regressions in a gdb testsuite.

llvm-svn: 103226

Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.

llvm-svn: 103218

 - This fixes "leal 0, %eax", for example.

llvm-svn: 103205

llvm-svn: 103199

and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196

we don't currently support relaxing them.

llvm-svn: 103195

doesn't have to guess.

llvm-svn: 103194

llvm-svn: 103193

llvm-svn: 103185

(replacing the previous patch for the same issue).

llvm-svn: 103183

llvm-svn: 103181

llvm-svn: 103179

at the token level. Consider the following horrible test case:

  a = 1
  .globl $a
  movl ($a), %eax
  movl $a, %eax
  movl $$a, %eax

llvm-svn: 103178

Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.

llvm-svn: 103172

with the fix in 103157.

%reg1039:1<def> = VMOVS %S1<kill>, pred:14, pred:%reg0
is not coalescable since none of the super-registers of S1 are in reg1039's
register class: DPR_VFP2. But it is still a legal copy instruction so it should
not assert.

llvm-svn: 103170

llvm-svn: 103163

   Reverse-merging r103156 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMRegisterInfo.h
U    lib/Target/ARM/ARMBaseRegisterInfo.cpp
U    lib/Target/ARM/ARMBaseInstrInfo.cpp
U    lib/Target/ARM/ARMRegisterInfo.td

llvm-svn: 103159

automatic syscall restarting is disabled.

Also, fix the build on systems which don't define EWOULDBLOCK.

llvm-svn: 103158

llvm-svn: 103157

Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.

llvm-svn: 103156

llvm-svn: 103155

llvm-svn: 103154

EAGAIN and EWOULDBLOCK are used here.

Also, handle the case where a write call is interrupted after
some data has already been written.

llvm-svn: 103153

llvm-svn: 103145

Users can write broken code that emits the same label twice with asm renaming,
detect this and emit a fatal backend error instead of aborting.

llvm-svn: 103140

llvm-svn: 103139

support a new bottom-up mode.

llvm-svn: 103138

allow $ at the start of a symbol name.

llvm-svn: 103137

instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136

of just letting them inherit the debug locations of adjacent instructions.

Debug info should aim to be either accurate or absent.

llvm-svn: 103135

llvm-svn: 103133

that was causing PC-relative branch targets to be
evaluated incorrectly.  Also added support for
checking operand values to the llvm-mc tester.

llvm-svn: 103128

llvm-svn: 103126

Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order.

llvm-svn: 103124

user's source, so don't arbitrarily assign them a debug location.

llvm-svn: 103121

Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.

llvm-svn: 103119

This fixes the compile-time regressions seen in last night's tests.

llvm-svn: 103118

writing them.
 - <rdar://problem/7885351> integrated assembler broken for i386 objc code

llvm-svn: 103112

llvm-svn: 103111

llvm-svn: 103110