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  1. Sep 06, 2012
  2. Sep 05, 2012
  3. Sep 04, 2012
    • Jakob Stoklund Olesen's avatar
      Typo. · d92e2bc2
      Jakob Stoklund Olesen authored
      llvm-svn: 163154
      d92e2bc2
    • Jakob Stoklund Olesen's avatar
      Actually use the MachineOperand field for isRegTiedToDefOperand(). · 9fceda74
      Jakob Stoklund Olesen authored
      The MachineOperand::TiedTo field was maintained, but not used.
      
      This patch enables it in isRegTiedToDefOperand() and
      isRegTiedToUseOperand() which are the actual functions use by the
      register allocator.
      
      llvm-svn: 163153
      9fceda74
    • Jakob Stoklund Olesen's avatar
      Move tie checks into MachineVerifier::visitMachineOperand. · c7579cdd
      Jakob Stoklund Olesen authored
      llvm-svn: 163152
      c7579cdd
    • Jakob Stoklund Olesen's avatar
      Allow tied uses and defs in different orders. · 0a09da83
      Jakob Stoklund Olesen authored
      After much agonizing, use a full 4 bits of precious MachineOperand space
      to encode this. This uses existing padding, and doesn't grow
      MachineOperand beyond its current 32 bytes.
      
      This allows tied defs among the first 15 operands on a normal
      instruction, just like the current MCInstrDesc constraint encoding.
      Inline assembly needs to be able to tie more than the first 15 operands,
      and gets special treatment.
      
      Tied uses can appear beyond 15 operands, as long as they are tied to a
      def that's in range.
      
      llvm-svn: 163151
      0a09da83
    • Preston Gurd's avatar
      Generic Bypass Slow Div · cdf540d5
      Preston Gurd authored
      - CodeGenPrepare pass for identifying div/rem ops
      - Backend specifies the type mapping using addBypassSlowDivType
      - Enabled only for Intel Atom with O2 32-bit -> 8-bit
      - Replace IDIV with instructions which test its value and use DIVB if the value
      is positive and less than 256.
      - In the case when the quotient and remainder of a divide are used a DIV
      and a REM instruction will be present in the IR. In the non-Atom case
      they are both lowered to IDIVs and CSE removes the redundant IDIV instruction,
      using the quotient and remainder from the first IDIV. However,
      due to this optimization CSE is not able to eliminate redundant
      IDIV instructions because they are located in different basic blocks.
      This is overcome by calculating both the quotient (DIV) and remainder (REM)
      in each basic block that is inserted by the optimization and reusing the result
      values when a subsequent DIV or REM instruction uses the same operands.
      - Test cases check for the presents of the optimization when calculating
      either the quotient, remainder,  or both.
      
      Patch by Tyler Nowicki!
      
      llvm-svn: 163150
      cdf540d5
  4. Sep 03, 2012
  5. Sep 02, 2012
  6. Sep 01, 2012
  7. Aug 31, 2012
  8. Aug 30, 2012
    • Nadav Rotem's avatar
      · ea973bda
      Nadav Rotem authored
      Currently targets that do not support selects with scalar conditions and vector operands - scalarize the code. ARM is such a target
      because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR
      to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2).
      
      rdar://12201387
      
      llvm-svn: 162926
      ea973bda
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