llvm-svn: 96990

llvm-svn: 96983

three or four registers and VLD2 (multiple two-element structures) which loads
memory into two double-spaced registers.

A8.6.307 & A8.6.310

llvm-svn: 96980

llvm-svn: 96977

disables load folding at -O0.

llvm-svn: 96973

The MicroBlaze is a highly configurable 32-bit soft-microprocessor for
use on Xilinx FPGAs. For more information see:
http://www.xilinx.com/tools/microblaze.htm
http://en.wikipedia.org/wiki/MicroBlaze

The current LLVM MicroBlaze backend generates assembly which can be
compiled using the an appropriate binutils assembler.

llvm-svn: 96969

llvm-svn: 96964

llvm-svn: 96960

llvm-svn: 96954

llvm-svn: 96943

llvm-svn: 96942

llvm-svn: 96903

then use it as an MMX register (!?).

llvm-svn: 96901

though some look dubious afaict, these are all ok.

llvm-svn: 96899

place where an i32 imm was required, the old isel just got lucky.

This fixes CodeGen/X86/x86-64-and-mask.ll

llvm-svn: 96894

llvm-svn: 96885

llvm-svn: 96871

don't alis it in the MMX .td file with a different width,
split into two X86ISD opcodes.  This fixes an x86 testcase.

llvm-svn: 96859

(immediate #0) for disassembly only.

A8.6.283, A8.6.285, A8.6.287, A8.6.290

llvm-svn: 96856

llvm-svn: 96854

llvm-svn: 96852

about ownership and update policies.  It isn't clear why it is doing all
this lowering at isel time instead of in legalize.  This fixes fcmp64.ll

llvm-svn: 96849

A8.6.281

llvm-svn: 96838

126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.

llvm-svn: 96822

llvm-svn: 96818

value.

Thumb2 uses the tADJCALLSTACK* instructions, and doesn't need t2 versions, so
remove the FIXME entry.

llvm-svn: 96817

llvm-svn: 96811

llvm-svn: 96810

for disassembly only.

llvm-svn: 96806

o signed/unsigned add/subtract
o signed/unsigned halving add/subtract
o unsigned sum of absolute difference [and accumulate]
o signed/unsigned saturate
o signed multiply accumulate/subtract [long] dual

llvm-svn: 96795

during a tail call. A parameter might overwrite this stack slot during the tail
call. 

The sequence during a tail call is:
1.) load return address to temp reg
2.) move parameters (might involve storing to return address stack slot)
3.) store return address to new location from temp reg

If the stack location is marked immutable CodeGen can colocate load (1) with the
store (3).

This fixes bug 6225.

llvm-svn: 96783

llvm-svn: 96778

SSE min and max instructions. The real thing this code needs to be
concerned about is negative zero.

Update the sse-minmax.ll test accordingly, and add tests for
-enable-unsafe-fp-math mode as well.

llvm-svn: 96775

create an X86ISD::Cmp node with result type i64 on the 
CodeGen/X86/shift-i256.ll testcase and the new isel was assert on it
downstream.

llvm-svn: 96768

llvm-svn: 96763

It turned out that we failed to emit proper symbol stubs on non-x86/darwin for ages (we emitted a reference to a stub, but no stub was emitted). The code inside x86-32/macho target objfile lowering should actually be the generic one - move it there.

This (I really, really hope) should fix EH issues on ppc/darwin
and arm/darwin.

llvm-svn: 96755

and another taking a raw_ostream, but otherwise identical.  Use raw_ostream everywhere.

llvm-svn: 96746

This fixes PR6348

llvm-svn: 96734

llvm-svn: 96720

handled in ARMInstPrinter.cpp.

And added PLD/PLDW/PLI (Preload Data/Instruction) for disassembly only.

llvm-svn: 96719