- Mar 08, 2012
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Andrew Trick authored
llvm-svn: 152262
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Andrew Trick authored
implement their own MachineScheduler. llvm-svn: 152261
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Andrew Trick authored
llvm-svn: 152260
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Andrew Trick authored
llvm-svn: 152259
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Andrew Trick authored
ScheduleDAGInstrs will be the main interface for MI-level schedulers. Make sure it's readable: one page of protected fields, one page of public methids. llvm-svn: 152258
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Andrew Trick authored
llvm-svn: 152257
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Andrew Trick authored
ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted. llvm-svn: 152256
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Andrew Trick authored
We had half the API with one convention, half with another. Now was a good time to clean it up. llvm-svn: 152255
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- Mar 07, 2012
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Chandler Carruth authored
llvm-svn: 152221
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Chandler Carruth authored
This one is particularly annoying because the hashing algorithm is highly specialized, with a strange "equivalence" definition that subsets the fields involved. Still, this looks at the exact same set of data as the old code, but without bitwise or-ing over parts of it and other mixing badness. No functionality changed here. I've left a substantial fixme about the fact that there is a cleaner and more principled way to do this, but it requires making the equality definition actual stable for particular types... llvm-svn: 152218
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Bill Wendling authored
the DebugLoc information can be maintained throughout by grabbing the DebugLoc before the RemoveBranch and then passing the result to the InsertBranch. Patch by Andrew Stanford-Jason! llvm-svn: 152212
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Andrew Trick authored
llvm-svn: 152210
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Andrew Trick authored
llvm-svn: 152209
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Andrew Trick authored
ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. llvm-svn: 152208
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Andrew Trick authored
llvm-svn: 152207
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Andrew Trick authored
ScheduleDAG has nothing to do with how the instructions are scheduled. llvm-svn: 152206
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Andrew Trick authored
ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152205
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Andrew Trick authored
ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152204
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Andrew Trick authored
llvm-svn: 152203
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Andrew Trick authored
llvm-svn: 152178
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Andrew Trick authored
Soon, ScheduleDAG will not refer to the BB. llvm-svn: 152177
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Andrew Trick authored
llvm-svn: 152176
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Andrew Trick authored
llvm-svn: 152175
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Andrew Trick authored
llvm-svn: 152174
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Andrew Trick authored
llvm-svn: 152173
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Andrew Trick authored
llvm-svn: 152172
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Eric Christopher authored
as well as completely defined classes. This fixes rdar://10956070 llvm-svn: 152171
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Evan Cheng authored
Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation). llvm-svn: 152162
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- Mar 06, 2012
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Jakob Stoklund Olesen authored
llvm-svn: 152153
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Evan Cheng authored
llvm-svn: 152089
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Owen Anderson authored
Make it possible for a target to mark FSUB as Expand. This requires providing a default expansion (FADD+FNEG), and teaching DAGCombine not to form FSUBs post-legalize if they are not legal. llvm-svn: 152079
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- Mar 05, 2012
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Jim Grosbach authored
Used to allow context sensitive printing of super-register or sub-register references. llvm-svn: 152043
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Bill Wendling authored
Patch by Sean Silva! llvm-svn: 152042
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Craig Topper authored
llvm-svn: 152016
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- Mar 04, 2012
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Jakob Stoklund Olesen authored
The first def of a virtual register cannot also read the register. Assert on such bad machine code instead of trying to fix it. TwoAddressInstructionPass should never create code like that. llvm-svn: 152010
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Jakob Stoklund Olesen authored
We are already setting <undef> flags, and that is good enough. The <imp-def> operands don't mean anything any more. llvm-svn: 152009
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Craig Topper authored
llvm-svn: 152001
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Craig Topper authored
llvm-svn: 151998
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Craig Topper authored
llvm-svn: 151996
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- Mar 02, 2012
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Eric Christopher authored
llvm-svn: 151875
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