Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.

Patch by Johnny Chen.

llvm-svn: 84572

Patch by Johnny Chen.

llvm-svn: 84570

no functionality change.

llvm-svn: 84567

by ignoring all implicit regs when lowering.

llvm-svn: 84566

llvm-svn: 84565

llvm-svn: 84563

llvm-svn: 84562

llvm-svn: 84561

like:

@ BB#1:
	.align	2
LCPI1_0:
	.long	L_.str-(LPC0+8)

Note that proper indentation of the label :)

llvm-svn: 84558

appropriate restore location for the spill as well as perform the actual
save and restore.

The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.

llvm-svn: 84554

llvm-svn: 84553

_main:
	stmsp! sp!, {r7, lr}
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, [sp]
	ldr r0, LCPI1_0
	bl _printf
	ldr r0, [sp]
	mov sp, r7
	ldmsp! sp!, {r7, pc}

Note the unhappy ldm/stm because of modifiers being ignored.

llvm-svn: 84546

broken makefile deps :(

llvm-svn: 84544

_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, [sp]
	ldr r0, LCPI1_0
	bl _printf
	ldr r0, [sp]
	mov sp, r7
	ldm , 

llvm-svn: 84543

lowering stuff.  We can now compile hello world to:

_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, 
	ldr r0, 
	bl _printf
	ldr r0, 
	mov sp, r7
	ldm , 

Almost looks like arm code :)

llvm-svn: 84542

llvm-svn: 84540

llvm-svn: 84536

_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, 

llvm-svn: 84535

we abort:

_main:
	stm , 
	mov r7, sp
	sub sp, sp, 
	mov r0, 
	str r0, 

llvm-svn: 84532

llvm-svn: 84531

through mcinst lowering -> mcinstprinter, when llc is passed
the -enable-arm-mcinst-printer flag.  Currently this
is very "aborty".

llvm-svn: 84530

"something" when printing MCInsts, it will just be missing all the 
operand info.

llvm-svn: 84528

llvm-svn: 84527

All of these "subreg32" modifier instructions are handled
explicitly by the MCInst lowering phase.  If they got to
the asmprinter, they would explode.  They should eventually
be replace with correct use of subregs.

llvm-svn: 84526

llvm-svn: 84521

llvm-svn: 84520

llvm-svn: 84519

llvm-svn: 84513

llvm-svn: 84512

llvm-svn: 84510

llvm-svn: 84509

llvm-svn: 84508

llvm-svn: 84506

LLC was scheduling compares before the adds causing wrong branches to be taken
in programs, resulting in misoptimized code wherever atomic adds where used.

llvm-svn: 84485

llvm-svn: 84459

llvm-svn: 84431

llvm-svn: 84425

stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot 
move above a store of spill slot #2. 
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.

llvm-svn: 84424

llvm-svn: 84411

Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues.

llvm-svn: 84326