doesn't have to guess.

llvm-svn: 103194

llvm-svn: 103193

llvm-svn: 103185

(replacing the previous patch for the same issue).

llvm-svn: 103183

llvm-svn: 103181

llvm-svn: 103179

at the token level. Consider the following horrible test case:

  a = 1
  .globl $a
  movl ($a), %eax
  movl $a, %eax
  movl $$a, %eax

llvm-svn: 103178

Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.

llvm-svn: 103172

with the fix in 103157.

%reg1039:1<def> = VMOVS %S1<kill>, pred:14, pred:%reg0
is not coalescable since none of the super-registers of S1 are in reg1039's
register class: DPR_VFP2. But it is still a legal copy instruction so it should
not assert.

llvm-svn: 103170

llvm-svn: 103163

   Reverse-merging r103156 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMRegisterInfo.h
U    lib/Target/ARM/ARMBaseRegisterInfo.cpp
U    lib/Target/ARM/ARMBaseInstrInfo.cpp
U    lib/Target/ARM/ARMRegisterInfo.td

llvm-svn: 103159

automatic syscall restarting is disabled.

Also, fix the build on systems which don't define EWOULDBLOCK.

llvm-svn: 103158

llvm-svn: 103157

Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.

llvm-svn: 103156

llvm-svn: 103155

llvm-svn: 103154

EAGAIN and EWOULDBLOCK are used here.

Also, handle the case where a write call is interrupted after
some data has already been written.

llvm-svn: 103153

llvm-svn: 103145

Users can write broken code that emits the same label twice with asm renaming,
detect this and emit a fatal backend error instead of aborting.

llvm-svn: 103140

llvm-svn: 103139

support a new bottom-up mode.

llvm-svn: 103138

allow $ at the start of a symbol name.

llvm-svn: 103137

instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136

of just letting them inherit the debug locations of adjacent instructions.

Debug info should aim to be either accurate or absent.

llvm-svn: 103135

llvm-svn: 103133

that was causing PC-relative branch targets to be
evaluated incorrectly.  Also added support for
checking operand values to the llvm-mc tester.

llvm-svn: 103128

llvm-svn: 103126

Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order.

llvm-svn: 103124

user's source, so don't arbitrarily assign them a debug location.

llvm-svn: 103121

Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.

llvm-svn: 103119

This fixes the compile-time regressions seen in last night's tests.

llvm-svn: 103118

writing them.
 - <rdar://problem/7885351> integrated assembler broken for i386 objc code

llvm-svn: 103112

llvm-svn: 103111

llvm-svn: 103110

llvm-svn: 103109

Microoptimize Twine's with unsigned and int to not pin their value to
the stack.  This saves stack space in common cases and allows mem2reg
in the caller.  A simple example is:

void foo(const Twine &);
void bar(int x) {
  foo("xyz: " + Twine(x));
}

Before:

__Z3bari:
	subq	$40, %rsp
	movl	%edi, 36(%rsp)
	leaq	L_.str3(%rip), %rax
	leaq	36(%rsp), %rcx
	leaq	8(%rsp), %rdi
	movq	%rax, 8(%rsp)
	movq	%rcx, 16(%rsp)
	movb	$3, 24(%rsp)
	movb	$7, 25(%rsp)
	callq	__Z3fooRKN4llvm5TwineE
	addq	$40, %rsp
	ret

After:

__Z3bari:
	subq	$24, %rsp
	leaq	L_.str3(%rip), %rax
	movq	%rax, (%rsp)
	movslq	%edi, %rax
	movq	%rax, 8(%rsp)
	movb	$3, 16(%rsp)
	movb	$7, 17(%rsp)
	leaq	(%rsp), %rdi
	callq	__Z3fooRKN4llvm5TwineE
	addq	$24, %rsp
	ret

It saves 16 bytes of stack and one instruction in this case.

llvm-svn: 103107

llvm-svn: 103104

llvm-svn: 103103

Teach liveintervalanalysis about virtual registers which are defined by reg_sequence instructions that are formed by registers defined by distinct instructions. e.g.
80      %reg1041:6<def> = VSHRNv4i16 %reg1034<kill>, 12, pred:14, pred:%reg0
. . .
120     %reg1041:5<def> = VSHRNv4i16 %reg1039<kill>, 12, pred:14, pred:%reg0

llvm-svn: 103102

llvm-svn: 103095