Make dllexport directives come out in determinstic order.

llvm-svn: 82381

llvm-svn: 82355

llvm-svn: 82314

Fix PR4926. When target hook EmitInstrWithCustomInserter() insert new basic blocks and update CFG, it should also inform sdisel of the changes so the phi source operands will come from the right basic blocks.

llvm-svn: 82311

Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that sdisel will use to properly complete phi nodes.
Not functionality change yet.

llvm-svn: 82273

causes the "../foo" to not find the file

llvm-svn: 82270

getSymbolForDwarfGlobalReference is smart enough to know that it 
needs to register the stub it references with MachineModuleInfoMachO,
so that it gets emitted at the end of the file.

Move stub emission from X86ATTAsmPrinter::doFinalization to the
new X86ATTAsmPrinter::EmitEndOfAsmFile asmprinter hook.  The important
thing here is that EmitEndOfAsmFile is called *after* the ehframes are
emitted, so we get all the stubs.

This allows us to remove a gross hack from the asmprinter where it would
"just know" that it needed to output stubs for personality functions.
Now this is all driven from a consistent interface.

The testcase change is just reordering the expected output now that the
stubs come out after the ehframe instead of before.

This also unblocks other changes that Bill wants to make.

llvm-svn: 82269

on x86, to avoid explicit test instructions. A few existing tests changed
due to arbitrary register allocation differences.

llvm-svn: 82263

carry bit) instructions to the Intel instruction
tables.

llvm-svn: 82260

llvm-svn: 82235

currently unused.

llvm-svn: 82157

as part string parsing) instructions to the Intel
instruction tables.

llvm-svn: 82089

instructions to the Intel instruction tables.

llvm-svn: 82084

instruction tables.

llvm-svn: 82083

to the Intel instruction tables.

llvm-svn: 82081

llvm-svn: 82054

and use MachineModuleInfoMachO instead.

llvm-svn: 82022

llvm-svn: 82020

stuff common across all macho targets.

llvm-svn: 82018

llvm-svn: 82011

the global variable list only happen for COFF targets.

llvm-svn: 82010

we have MCInstPrinter.

llvm-svn: 82006

llvm-svn: 81999

trying to create RMW opportunities in the x86 backend.  This can cause a 
cycle to appear in the graph, since the other uses may eventually feed into
the TokenFactor we are sinking the load below.

llvm-svn: 81996

frame, to the Intel instruction tables.

llvm-svn: 81995

the Intel instruction tables.

The patterns will stay blank because ADD reg, reg
is faster, but having the encoding available is
useful for the disassembler.

llvm-svn: 81994

covered by other definitions.

llvm-svn: 81992

Eliminate the PersonalityPrefix/Suffix & NeedsIndirectEncoding
fields from MAI: they aren't part of the asm syntax, they are
related to the structure of the object file.

To replace their functionality, add a new 
TLOF::getSymbolForDwarfGlobalReference method which asks targets
to decide how to reference a global from EH in a pc-relative way.

The default implementation just returns the symbol.  The default
darwin implementation references the symbol through an indirect
$non_lazy_ptr stub.  The bizarro x86-64 darwin specialization
handles the weird "foo@GOTPCREL+4" hack.

DwarfException.cpp now uses this to emit the reference to the
symbol in the right way, and this also eliminates another 
horrible hack from DwarfException.cpp:

-    if (strcmp(MAI->getPersonalitySuffix(), "+4@GOTPCREL"))
-      O << "-" << MAI->getPCSymbol();

llvm-svn: 81991

All of these do not have patterns (they're for the
disassembler).

Many of the floating-point instructions will probably
be rolled into definitions that have patterns, and may
eventually be superseded by mdefs.  So I put them
together and left a comment.

llvm-svn: 81979

code in other segments) to the Intel instruction
tables.

llvm-svn: 81953

llvm-svn: 81923

Intel tables, where the source operand is
specified by the R/M field and the destination
operand by the Reg field.

llvm-svn: 81914

to the Intel register table.
Added 16- and 64-bit MOVs to and from the segment
registers to the Intel instruction tables.

llvm-svn: 81895

interrupt instruction, which shouldn't arise any other way).  0xcd is
also used by JITMemoryManager to initialize the buffer to garbage,
which means it could appear following a noreturn call even when
that is not a stub, confusing X86CompilationCallback2.  PR 4929.

llvm-svn: 81888

values to machineinstrs.

llvm-svn: 81886

has multiple uses, as one of the other uses may be on a path
to a different node above the callseq_start, because that
leads to a cyclic graph. This problem is exposed when
-combiner-global-alias-analysis is used. This fixes PR4880.

llvm-svn: 81821

versions of CALL and JMP with segmented addresses
provided in-line, as pairs of immediates.

llvm-svn: 81818

its result if the condition is false.

llvm-svn: 81814

full AsmPrinter, and change TargetRegistry to keep track
of registered MCInstPrinters.

llvm-mc is still linking in the entire
target foo to get the code emitter stuff, but this is an
important step in the right direction.

llvm-svn: 81754

be a MCInstPrinter.

llvm-svn: 81746