llvm-svn: 27337

"vspltisb v0, 8" instead of a constant pool load.

llvm-svn: 27335

llvm-svn: 27331

llvm-svn: 27324

llvm-svn: 27322

llvm-svn: 27321

No functionality change.

llvm-svn: 27320

alignment of a packed type. This is obviously wrong. Added a workaround that
returns the size of the packed type as its alignment. The correct fix would
be to return a target dependent alignment value provided via TargetLowering
(or some other interface).

llvm-svn: 27319

llvm-svn: 27315

INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.

llvm-svn: 27314

llvm-svn: 27310

llvm-svn: 27308

llvm-svn: 27307

llvm-svn: 27306

llvm-svn: 27305

from a 128-bit vector.

llvm-svn: 27304

llvm-svn: 27303

llvm-svn: 27302

llvm-svn: 27291

identical instructions into a single instruction.  For example, for:

void test(vector float *x, vector float *y, int *P) {
  int v = vec_any_out(*x, *y);
  *x = (vector float)vec_cmpb(*x, *y);
  *P = v;
}

we now generate:

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v0, v1, v0
        mfcr r4, 2
        stvx v0, 0, r3
        rlwinm r3, r4, 27, 31, 31
        xori r3, r3, 1
        stw r3, 0(r5)
        mtspr 256, r2
        blr

instead of:

_test:
        mfspr r2, 256
        oris r6, r2, 57344
        mtspr 256, r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v2, v1, v0
        mfcr r4, 2
***     vcmpbfp v0, v1, v0
        rlwinm r4, r4, 27, 31, 31
        stvx v0, 0, r3
        xori r3, r4, 1
        stw r3, 0(r5)
        mtspr 256, r2
        blr

Testcase here: CodeGen/PowerPC/vcmp-fold.ll

llvm-svn: 27290

llvm-svn: 27288

llvm-svn: 27287

predicates to VCMPo nodes.

llvm-svn: 27285

llvm-svn: 27284

llvm-svn: 27277

llvm-svn: 27276

llvm-svn: 27275

unpromoted element type.

llvm-svn: 27273

llvm-svn: 27272

llvm-svn: 27271

llvm-svn: 27270

llvm-svn: 27268

directly correspond to intrinsics.

llvm-svn: 27266

llvm-svn: 27265

Use pshufd, pshuhw, and pshulw to shuffle v4f32 if shufps doesn't match.
Use shufps to shuffle v4f32 if pshufd, pshuhw, and pshulw don't match.

llvm-svn: 27259

llvm-svn: 27257

llvm-svn: 27256

llvm-svn: 27255

For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.

llvm-svn: 27254

- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.

llvm-svn: 27252