Commits · 7b6475568d8449dd84ddc839181cfc0ac74a3e13 · Roger Ferrer / llvm-epi-0.8 · GitLab

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Oct 28, 2016
- AMDGPU: Add definitions for scalar store instructions · 7b647556
  Matt Arsenault authored Oct 28, 2016
  7b647556
- [NVPTX] Compute 'rem' using the result of 'div', if possible. · f0a80ba3
  Justin Lebar authored Oct 28, 2016
  f0a80ba3
- AMDGPU: Change check prefix in test · b5f2bb1a
  Matt Arsenault authored Oct 28, 2016
  b5f2bb1a
- AMDGPU: Diagnose using too many SGPRs · 4eae3019
  Matt Arsenault authored Oct 28, 2016
  4eae3019
- Handle non-~0 lane masks on live-in registers in LivePhysRegs · 2717175c
  Krzysztof Parzyszek authored Oct 28, 2016
  2717175c
- AMDGPU: Fix using incorrect private resource with no allocation · 08906a3c
  Matt Arsenault authored Oct 28, 2016
  08906a3c
- Implement vector count leading/trailing bytes with zero lsb and vector parity · e28a0fc7
  Nemanja Ivanovic authored Oct 28, 2016
  e28a0fc7
- Make swift calling convention test specific to armv7 · 6200b2b6
  Arnold Schwaighofer authored Oct 28, 2016
  6200b2b6
- [x86] add tests for missed umin/umax · 03a585e8
  Sanjay Patel authored Oct 28, 2016
  03a585e8
- More swift calling convention tests · 7f4b31c0
  Arnold Schwaighofer authored Oct 28, 2016
  7f4b31c0
- [Hexagon] Maintain kill flags through splitting in expand-condsets · 87a47be0
  Krzysztof Parzyszek authored Oct 28, 2016
  87a47be0
- Revert "[DAGCombiner] Add vector demanded elements support to computeKnownBits" · 5cee232b
  Juergen Ributzka authored Oct 28, 2016
  5cee232b
- AMDGPU/SI: Handle hazard with s_rfe_b64 · aea899e2
  Tom Stellard authored Oct 27, 2016
  aea899e2
- AMDGPU/SI: Handle hazard with sgpr lane selects for v_{read,write}lane · 04051b5f
  Tom Stellard authored Oct 27, 2016
  04051b5f
- AMDGPU/SI: Handle hazard with > 8 byte VMEM stores · b133fbb9
  Tom Stellard authored Oct 27, 2016
  b133fbb9
Oct 27, 2016
- AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizer · 30d30824
  Tom Stellard authored Oct 27, 2016
  30d30824
- [PPC] Adding the removed testcase again · 2492721c
  Ehsan Amiri authored Oct 27, 2016
  2492721c
- ARM: ensure that the Windows DBZ check is in range · 075d2e3c
  Saleem Abdulrasool authored Oct 27, 2016
  075d2e3c
- [mips] Do not allow -opt-bisect-limit to skip the PIC call optimization pass. · cfb005a0
  Vasileios Kalintiris authored Oct 27, 2016
  cfb005a0
- [X86][AVX512DQ] Improve lowering of MUL v2i64 and v4i64 · 820e1326
  Simon Pilgrim authored Oct 27, 2016
  820e1326
- [Hexagon] Do not expand ISD::SELECT for HVX vectors · 046da746
  Krzysztof Parzyszek authored Oct 27, 2016
  046da746
- [DAGCombiner] Add vector demanded elements support to computeKnownBits · 01e755ea
  Simon Pilgrim authored Oct 27, 2016
  01e755ea
- [ARM] Add newline char to test. · 09947a31
  Sam Parker authored Oct 27, 2016
  09947a31
- [ARM] Predicate UMAAL selection on hasDSP. · e7d9505c
  Sam Parker authored Oct 27, 2016
  e7d9505c
- AMDGPU: Fix SILoadStoreOptimizer when writes cannot be merged due register dependencies · 7b0e25b7
  Nicolai Haehnle authored Oct 27, 2016
  7b0e25b7
- [PowerPC] - No SExt/ZExt needed for count trailing zeros · 32b5fed6
  Nemanja Ivanovic authored Oct 27, 2016
  32b5fed6
Oct 26, 2016
- ARM: don't rely on push/pop reglists being in order when folding SP adjust. · a9cc3856
  Tim Northover authored Oct 26, 2016
  a9cc3856
- Do not assume that FP vector operands are never legalized by expanding · 275853e7
  Nemanja Ivanovic authored Oct 26, 2016
  275853e7
- [PowerPC] Implement vec_insert_exp builtins - llvm portion · 0f45998b
  Nemanja Ivanovic authored Oct 26, 2016
  0f45998b
- Fix test from r285217. · 96e5e16a
  Chad Rosier authored Oct 26, 2016
  96e5e16a
- [AArch64] Avoid materializing constant 1 when generating cneg instructions. · 0c621fda
  Chad Rosier authored Oct 26, 2016
  0c621fda
- AMDGPU: Refactor processor definition to use ISA version features · 94add85a
  Yaxun Liu authored Oct 26, 2016
  94add85a
- Reapply "AMDGPU: Don't use offen if it is 0" · 39787bdc
  Matt Arsenault authored Oct 26, 2016
  39787bdc
- AMDGPU/SI: Don't emit multi-dword flat memory ops when they might access scratch · f8e6eaff
  Tom Stellard authored Oct 26, 2016
  f8e6eaff
- AMDGPU/SI: Remove unnecessary run lines from test · 9daed22b
  Tom Stellard authored Oct 26, 2016
  9daed22b
- [X86] AVX512 fallback for floating-point scalar selects · aa3402b4
  Zvi Rackover authored Oct 26, 2016
  aa3402b4
- [AVX-512] Add scalar vfmsub/vfnmsub mask3 intrinsics · 812d3d30
  Craig Topper authored Oct 26, 2016
  812d3d30
- [Sparc] Don't overlap variable-sized allocas with other stack variables. · 2e64b8b7
  James Y Knight authored Oct 25, 2016
  2e64b8b7
- [DAGCombiner] Enable (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y),... · de86241a
  Simon Pilgrim authored Oct 25, 2016
  de86241a
Oct 25, 2016
- [X86][SSE] Regenerated known-bits test with srem->urem fix · daf82f5f
  Simon Pilgrim authored Oct 25, 2016
  daf82f5f