FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

llvm-svn: 101754

even if the element of the array has no size.

llvm-svn: 101662

in memory operands.  rdar://7874844

llvm-svn: 101661

llvm-svn: 101655

llvm-svn: 101648

llvm-svn: 101640

llvm-svn: 101639

llvm-svn: 101637

llvm-svn: 101636

const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635

MachineFunctionInfo subclasses.

llvm-svn: 101634

Also rename the classes appropriately. The CMake build already used these
names.

llvm-svn: 101631

i8 field when they really do not.  This fixes rdar://7840289

llvm-svn: 101629

llvm-svn: 101621

may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.

llvm-svn: 101615

llvm-svn: 101581

Probably the best way to know that all getOperand() calls have been handled
is to replace that API instead of updating.

llvm-svn: 101579

llvm-svn: 101573

llvm-svn: 101564

on it.

llvm-svn: 101563

case.  Also, the 0xFF hex literal involved in the shift for ESize64 should be
suffixed "ul" to preserve the shift result.

Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a
test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand().

llvm-svn: 101557

llvm-svn: 101538

llvm-svn: 101531

this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case.

llvm-svn: 101529

to the UAL syntax of LDCL<c>, instead.

Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().

llvm-svn: 101527

considered legal instructions.

Refs: A8.6.51 LDC, LDC2 (immediate) -- page A8-107, A8.6.58 LDR (immediate, ARM)
-- page A8-121, and A8.6.194 STR (immediate, ARM) -- page A8-395.

llvm-svn: 101524

with a fix for self-hosting

rotate CallInst operands, i.e. move callee to the back
of the operand array

the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary

llvm-svn: 101465

Adding support for dag combiner to promote operations for profit. This requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding.
x86 support is off by default. It can be enabled with -promote-16bit.

Work in progress.

llvm-svn: 101448

llvm-svn: 101446

llvm-svn: 101434

am2offset.  Modified the instruction table entry and added a new test case.

llvm-svn: 101415

Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2.

llvm-svn: 101410

with a fix

rotate CallInst operands, i.e. move callee to the back
of the operand array

the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary

llvm-svn: 101397

ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908

llvm is generating poor code for dynamic alloca, I'll fix that later.

llvm-svn: 101383

llvm-svn: 101382

llvm-svn: 101379

can't be static.

llvm-svn: 101377

llvm-svn: 101376

llvm-svn: 101368

of the operand array

the motivation for this patch are laid out in my mail to llvm-commits:
more efficient access to operands and callee, faster callgraph-construction,
smaller compiler binary

llvm-svn: 101364