Invalid operation is signaled if the operand of these instructions is NaN.

llvm-svn: 154545

Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.

llvm-svn: 152997

llvm-svn: 152450

llvm-svn: 151645

Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.

llvm-svn: 151630

llvm-svn: 151625

the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.

Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.

rdar://8979299

llvm-svn: 151623

needed to emit a 64-bit gp-relative relocation entry. Make changes necessary
for emitting jump tables which have entries with directive .gpdword. This patch
does not implement the parts needed for direct object emission or JIT.

llvm-svn: 149668

llvm-svn: 146232

- Modify lowering of global TLS address nodes.
- Modify isel of ThreadPointer.
- Wrap target global TLS address nodes that are operands of loads with WrapperPIC. 
- Remove Mips-specific DAG nodes TlsGd, TprelHi and TprelLo, which can be
  substituted with other existing nodes.

llvm-svn: 146175

instruction definitions.

llvm-svn: 143989

llvm-svn: 143213

Mips64.

llvm-svn: 141618

llvm-svn: 140569

with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons.  Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all").  Patch mostly by
Nadav Rotem.

llvm-svn: 139159

llvm-svn: 137831

llvm-svn: 137804

llvm-svn: 137515

llvm-svn: 136283

llvm-svn: 135537

Part of rdar://9643582

llvm-svn: 134084

llvm-svn: 133494

llvm-svn: 132777

dynamically allocated stack area was not set.

llvm-svn: 132758

llvm-svn: 132444

nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions.
The intrinsics are implemented by creating pseudo-instructions, which are
then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter.

Patch by Sasa Stankovic.

llvm-svn: 132323

Dynamic, Initial Exec and Local Exec TLS models.

Patch by Sasa Stankovic

llvm-svn: 132322

Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240

been defined in MipsInstrFPU.td.

llvm-svn: 132076

llvm-svn: 132074

llvm-svn: 131012

llvm-svn: 129612

Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.

llvm-svn: 129606

Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions.

llvm-svn: 129594

llvm-svn: 128650

llvm-svn: 127034

llvm-svn: 127027

llvm-svn: 127003

llvm-svn: 123760

Remove target specific node MipsISD::CMov, which is not used because all conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again

llvm-svn: 121164