generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026

make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs

llvm-svn: 146024

llvm-svn: 146023

llvm-svn: 146022

llvm-svn: 146021

The block offset can be computed from the previous block. That is more
robust than keeping track of a delta.

Eliminate one redundant AdjustBBOffsetsAfter call.

llvm-svn: 146018

These fields are not used for anything yet.

llvm-svn: 146017

The TokenAlias handling of data type suffices renders these unnecessary.

llvm-svn: 146010

llvm-svn: 146008

Data type suffix aliasing. Previously handled via lots of instruction
aliases. Cleanup of those forthcoming.

rdar://10435076

llvm-svn: 146007

No functional change is intended.

llvm-svn: 146005

llvm-svn: 146003

make the addend fixup code a bit more generic

Patch by Jack Carter.

llvm-svn: 145998

No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.

llvm-svn: 145994

This caused more offset errors.

llvm-svn: 145980

llvm-svn: 145976

1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975

This pseudo-instruction contains a .align directive in its expansion, so
the total size may vary by 2 bytes.

It is too difficult to accurately keep track of this alignment
directive, just use the worst-case size instead.

llvm-svn: 145971

ARMConstantIslandPass may sometimes leave empty constant islands behind
(it really shouldn't). Remove the alignment from the empty islands so
the size calculations are still correct.

This should fix the many Thumb1 assembler errors in the nightly test
suite.

The reduced test case for this problem is way too big. That is to be
expected for ARMConstantIslandPass bugs.

<rdar://problem/10534709>

llvm-svn: 145970

llvm-svn: 145969

* Rename variables to reflect what they're actually used for.

llvm-svn: 145968

llvm-svn: 145961

llvm-svn: 145960

llvm-svn: 145954

llvm-svn: 145952

llvm-svn: 145947

llvm-svn: 145946

llvm-svn: 145929

Fix a bunch of SSE/AVX patterns to use v2i64/v4i64 loads since all other integer vector loads are promoted to those.

llvm-svn: 145927

llvm-svn: 145926

Clean up some of the shuffle decoding code for UNPCK instructions. Add instruction commenting for AVX/AVX2 forms for integer UNPCKs.

llvm-svn: 145924

Same as r145922, just for ARM mode.

llvm-svn: 145923

Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.

rdar://10532439

llvm-svn: 145922

Merge isSHUFPMask and isCommutedSHUFPMask into single function that can do both. Do the same for the 256-bit version. Use loops to reduce size of isVSHUFPYMask. Fix test cases that were incorrectly passing due to isCommutedSHUFPMask not checking for the vector being 128-bit. This caused some 256-bit shuffles to be incorrectly commuted.

llvm-svn: 145921

Using encoding T1 for offset of #0 and encoding T2 for #-0.

rdar://10532413

llvm-svn: 145919

llvm-svn: 145912

llvm-svn: 145910

llvm-svn: 145896

llvm-svn: 145895

llvm-svn: 145894