Commits · 7fce867856934ae09bfd3d4dac0552249e1d03f2 · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Aug 14, 2019
- Fix cppcheck + MSVC analyzer uninitialized member variable warning. NFCI. · 7fce8678
  Simon Pilgrim authored Aug 14, 2019
  7fce8678
- [DebugInfo] MCP: collect and update DBG_VALUEs encountered in local block · 90c2794b
  Jeremy Morse authored Aug 14, 2019
  90c2794b
Aug 13, 2019
- [GISel] Pass MachineRegisterInfo by const reference to matcher. · b058249a
  Mark Lacey authored Aug 13, 2019
  b058249a
- GlobalISel: Partially implement fewerElementsVector G_UNMERGE_VALUES · 28215caa
  Matt Arsenault authored Aug 13, 2019
  28215caa
- GlobalISel: Implement lower for G_SHUFFLE_VECTOR · 690645bd
  Matt Arsenault authored Aug 13, 2019
  690645bd
- GlobalISel: Change representation of shuffle masks · 5af9cf04
  Matt Arsenault authored Aug 13, 2019
  5af9cf04
- [CodeGen][SelectionDAG] More efficient code for X % C == 0 (SREM case) · 67659430
  Roman Lebedev authored Aug 13, 2019
  67659430
- [GlobalISel] Make the InstructionSelector instance non-const, allowing state to be maintained. · e14c91b7
  Amara Emerson authored Aug 13, 2019
  e14c91b7
- Eliminate implicit Register->unsigned conversions in VirtRegMap. NFC · a58a2751
  Daniel Sanders authored Aug 13, 2019
  a58a2751
Aug 09, 2019
- [globalisel] Add G_SEXT_INREG · e9a57c2b
  Daniel Sanders authored Aug 09, 2019
  e9a57c2b
- GlobalISel: pack various parameters for lowerCall into a struct. · e1a5f668
  Tim Northover authored Aug 09, 2019
  e1a5f668
Aug 08, 2019
- [GISel][NFC]: Make members of CombinerHelper accessible in derived classes · 277583ec
  Aditya Nandakumar authored Aug 08, 2019
  277583ec
- Recommit "[MS] Emit S_HEAPALLOCSITE debug info in Selection DAG" · 0b870b96
  Amy Huang authored Aug 07, 2019
  0b870b96
Aug 07, 2019
- GlobalISel: factor common code from translateCall and translateInvoke. NFC. · 3c10f346
  Tim Northover authored Aug 07, 2019
  3c10f346
Aug 06, 2019
- [GISel]: Fix trivial build breakage · 6bbfde5c
  Aditya Nandakumar authored Aug 06, 2019
  6bbfde5c
- [GISel]: Add GISelKnownBits analysis · c8ac029d
  Aditya Nandakumar authored Aug 06, 2019
  c8ac029d
- [globalisel] Allow SrcOp to convert an APInt and render it as an immediate... · d9934d49
  Daniel Sanders authored Aug 06, 2019
  d9934d49
- [Strict FP] Allow custom operation actions · 7b24dd74
  Ulrich Weigand authored Aug 06, 2019
  7b24dd74
- [SelectionDAG] Extend base addressing modes supported by MGATHER/MSCATTER · ced419f4
  Cullen Rhodes authored Aug 06, 2019
  ced419f4
- CodeGen: Migration to using Register · f4d3113a
  Matt Arsenault authored Aug 06, 2019
  f4d3113a
- Fix another MSVC issue after 367965 · de406081
  Daniel Sanders authored Aug 06, 2019
  de406081
- Re-commit Register/MCRegister: Add conversion operators to avoid use of... · 269191ea
  Daniel Sanders authored Aug 06, 2019
  269191ea
- [GlobalISel][CallLowering] Rename isArgumentHandler() -> isIncomingArgumentHandler() · bc1172df
  Amara Emerson authored Aug 05, 2019
  bc1172df
Aug 05, 2019
- Revert Register/MCRegister: Add conversion operators to avoid use of implicit... · eac86ec2
  Daniel Sanders authored Aug 05, 2019
  eac86ec2
- [AArch64][GlobalISel] Inline tiny memcpy et al at -O0. · 85e5e28a
  Amara Emerson authored Aug 05, 2019
  85e5e28a
- Register/MCRegister: Add conversion operators to avoid use of implicit convert to unsigned. NFC · aa15ec3c
  Daniel Sanders authored Aug 05, 2019
  aa15ec3c
- [MVT][SVE] Map between scalable vector IR Type and VTs · 208d63ea
  Graham Hunter authored Aug 05, 2019
  208d63ea
- [LLVM][Alignment] Introduce Alignment Type · c97a3d15
  Guillaume Chatelet authored Aug 05, 2019
  c97a3d15
- [LLVM][Alignment] Introduce Alignment In CallingConv · 6c5fb61f
  Guillaume Chatelet authored Aug 05, 2019
  6c5fb61f
- Reland: Fix and test inter-procedural register allocation for ARM · 8ed8353f
  Oliver Stannard authored Aug 05, 2019
  8ed8353f
Aug 03, 2019
- Emit diagnostic if an inline asm constraint requires an immediate · 41a2847a
  Bill Wendling authored Aug 03, 2019
  41a2847a
- MCRegister/Register: DenseMapInfo should take `const T &` · 00879c3e
  Daniel Sanders authored Aug 03, 2019
  00879c3e
- Re-commit "[GlobalISel] Add legalization support for non-power-2 loads and stores"" · c835164a
  Amara Emerson authored Aug 02, 2019
  c835164a
- Revert Fix and test inter-procedural register allocation for ARM · 42618b27
  Douglas Yung authored Aug 02, 2019
  42618b27
Aug 02, 2019
- Use MCRegister in MCRegisterInfo's interfaces · e7694f34
  Daniel Sanders authored Aug 02, 2019
  e7694f34
- Add MCRegister and use it in MCRegisterClass::contains() · fae0a60a
  Daniel Sanders authored Aug 02, 2019
  fae0a60a
- [IPRA][ARM] Disable no-CSR optimisation for ARM · 4b7239eb
  Oliver Stannard authored Aug 02, 2019
  4b7239eb
- Fix and test inter-procedural register allocation for ARM · f6b00c27
  Oliver Stannard authored Aug 02, 2019
  f6b00c27
- Prevent vregs leaking into the MC layer via TargetRegisterClass::contains() · 1055a11d
  Daniel Sanders authored Aug 01, 2019
  1055a11d
- Finish moving TargetRegisterInfo::isVirtualRegister() and friends to... · 2bea69bf
  Daniel Sanders authored Aug 01, 2019
  2bea69bf