code for IV uses outside of loops that are not dominated by the latch block.
We should only convert these uses to use the post-inc value if they ARE
dominated by the latch block.

Also use a new LoopInfo method to simplify some code.

This fixes Transforms/LoopStrengthReduce/2005-09-12-UsesOutOutsideOfLoop.ll

llvm-svn: 23318

llvm-svn: 23315

        li r2, 0
LBB_test_1:     ; no_exit.2
        li r5, 0
        stw r5, 0(r3)
        addi r2, r2, 1
        addi r3, r3, 4
        cmpwi cr0, r2, 701
        blt cr0, LBB_test_1     ; no_exit.2
LBB_test_2:     ; loopexit.2.loopexit
        addi r2, r2, 1
        stw r2, 0(r4)
        blr
[zion ~/llvm]$ cat > ~/xx
Uses of IV's outside of the loop should use hte post-incremented version
of the IV, not the preincremented version.  This helps many loops (e.g. in sixtrack)
which used to generate code like this (this is the code from the
dont-hoist-simple-loop-constants.ll testcase):

_test:
        li r2, 0                 **** IV starts at 0
LBB_test_1:     ; no_exit.2
        or r5, r2, r2            **** Copy for loop exit
        li r2, 0
        stw r2, 0(r3)
        addi r3, r3, 4
        addi r2, r5, 1
        addi r6, r5, 2           **** IV+2
        cmpwi cr0, r6, 701
        blt cr0, LBB_test_1     ; no_exit.2
LBB_test_2:     ; loopexit.2.loopexit
        addi r2, r5, 2       ****  IV+2
        stw r2, 0(r4)
        blr

And now generated code like this:

_test:
        li r2, 1               *** IV starts at 1
LBB_test_1:     ; no_exit.2
        li r5, 0
        stw r5, 0(r3)
        addi r2, r2, 1
        addi r3, r3, 4
        cmpwi cr0, r2, 701     *** IV.postinc + 0
        blt cr0, LBB_test_1
LBB_test_2:     ; loopexit.2.loopexit
        stw r2, 0(r4)          *** IV.postinc + 0
        blr

llvm-svn: 23313

We used to emit this code for it:

_test:
        li r2, 1     ;; Value tying up a register for the whole loop
        li r5, 0
LBB_test_1:     ; no_exit.2
        or r6, r5, r5
        li r5, 0
        stw r5, 0(r3)
        addi r5, r6, 1
        addi r3, r3, 4
        add r7, r2, r5  ;; should be addi r7, r5, 1
        cmpwi cr0, r7, 701
        blt cr0, LBB_test_1     ; no_exit.2
LBB_test_2:     ; loopexit.2.loopexit
        addi r2, r6, 2
        stw r2, 0(r4)
        blr

now we emit this:

_test:
        li r2, 0
LBB_test_1:     ; no_exit.2
        or r5, r2, r2
        li r2, 0
        stw r2, 0(r3)
        addi r3, r3, 4
        addi r2, r5, 1
        addi r6, r5, 2   ;; whoa, fold those adds!
        cmpwi cr0, r6, 701
        blt cr0, LBB_test_1     ; no_exit.2
LBB_test_2:     ; loopexit.2.loopexit
        addi r2, r5, 2
        stw r2, 0(r4)
        blr

more improvement coming.

llvm-svn: 23306

llvm-svn: 23304

when storing to an 8-bit memory location), as most don't.

llvm-svn: 23303

llvm-svn: 23302

select (x < y), 1, 0 -> (x < y) incorrectly: the setcc returns i1 but the
select returned i32.  Add the zero extend as needed.

llvm-svn: 23301

llvm-svn: 23300

for FP as well.  This triggers a couple dozen times on 177.mesa (for example).

llvm-svn: 23299

with copies, leading to code like this:

       lwz r4, 380(r1)
       or r10, r4, r4    ;; Last use of r4

By teaching the PPC backend how to fold spills into copies, we now get this
code:

       lwz r10, 380(r1)

wow. :)

This reduces a testcase nate sent me from 1505 instructions to 1484.

Note that this could handle FP values but doesn't currently, for reasons
mentioned in the patch

llvm-svn: 23298

llvm-svn: 23297

are, simplify logic, and cause things to not be nested as deeply.  This also
uses MRI->areAliases instead of an explicit loop.

No functionality change, just code cleanup.

llvm-svn: 23296

as setcc and select next.

llvm-svn: 23295

llvm-svn: 23294

only add a reload live range once for the instruction.  This is one step
towards fixing a regalloc pessimization that Nate notice, but is later undone
by the spiller (so no code is changed).

llvm-svn: 23293

is zero.  This lets the register allocator elide some copies in some cases.

This implements CodeGen/PowerPC/rlwimi-commute.ll

llvm-svn: 23292

1. Add support for defining Pattern's, which can match expressions when there
   is no instruction that directly implements something.  Instructions usually
   implicitly define patterns.
2. Add support for defining SDNodeXForm's, which are node transformations.
   This seperates the concept of a node xform out from the existing predicate
   support.

Using this new stuff, we add a few instruction patterns, one for testing, and
two for OR/XOR by an arbitrary immediate.

llvm-svn: 23286

llvm-svn: 23283

llvm-svn: 23278

the rest of the instructions, add comment markers to seperate portions of
the file into logical parts

llvm-svn: 23277

llvm-svn: 23268

for matching signed 16-bit and shifted 16-bit ppc immediates

llvm-svn: 23267

llvm-svn: 23266

llvm-svn: 23263

llvm-svn: 23262

as well as fixing how we replace old values with new values.

llvm-svn: 23260

preserve livevar

llvm-svn: 23259

This restores all of stanford to being identical with and without the dag
combiner with the add folding turned off in sd.cpp.

llvm-svn: 23258

'' is not a recognized processor for this target (ignoring processor)

Default to "generic" instead of "" for the default CPU.

llvm-svn: 23257

'' is not a recognized processor for this target (ignoring processor)

instead of:

 is not a recognized processor for this target (ignoring processor)

llvm-svn: 23256

we were losing a node, causing an assertion to fail.  Now we eagerly delete
discovered CSE's, and provide an optional vector to keep track of these
discovered equivalences.

llvm-svn: 23255

that option for PowerPC's beta.

llvm-svn: 23253

are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts,
such as the PowerPC 970.

This speeds up 189.lucas from 81.99 to 32.64 seconds.

llvm-svn: 23250

llvm-svn: 23246

llvm-svn: 23245

generate the fun in-register fp<->long instructions.

llvm-svn: 23244

I have run so far when run before Legalize.  It still needs to pick up the
SetCC folds, and nodes that use SetCC.

llvm-svn: 23243

llvm-svn: 23241

llvm-svn: 23240