llvm-svn: 135343

Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode.  Update the ARM disassembler for this change.

llvm-svn: 135319

Remove VMOVDneon and VMOVQ, which are just aliases for VORR.  This continues to simplify the path towards an auto-generated disassembler.

llvm-svn: 135290

Remove unnecessary duplicate instruction definitions that simply overloaded the type of VEXT.  This can be achieved with a Pat definition, and is much more disassembler friendly.

llvm-svn: 135283

MSVC decorates (and distinguishes) "const" in mangler. It brought linkage error between "extern const" declarations and definitions.

llvm-svn: 135269

solution but it is a small step towards removing the horror that is
TargetAsmInfo.

llvm-svn: 135237

backend. Moved some MCAsmInfo files down into the MCTargetDesc
sublibraries, removed some (i suspect long) dead files from other parts
of the CMake build, etc. Also copied the include directory hack from the
Makefile.

Finally, updated the lib deps. I spot checked this, and think its
correct, but review appreciated there.

llvm-svn: 135234

Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.

llvm-svn: 135219

For example, "mlss r0, r1, r2, r3".

The MLS instruction does not have a flag-setting variant.

llvm-svn: 135203

llvm-svn: 135199

llvm-svn: 135198

llvm-svn: 135192

The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.

llvm-svn: 135189

registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184

Consolidate the individual declarations together for ease of reference. This
mirrors the organization in X86, as well, so is good for consistency. No
functional change.

llvm-svn: 135179

llvm-svn: 135169

ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.

llvm-svn: 135168

The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.

llvm-svn: 135156

Add instalias for default 'sy' option. Add tests.

llvm-svn: 135116

llvm-svn: 135112

Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".

llvm-svn: 135109

llvm-svn: 135107

Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode.  Switch ARM over to using that rather than its own special MCInstrDesc bits.

llvm-svn: 135106

Add range checking and testing for parsing and encoding of DBG instruction.

llvm-svn: 135102

llvm-svn: 135094

llvm-svn: 135093

llvm-svn: 135092

Combine redundant base classes and such. No indended functional change.

llvm-svn: 135085

llvm-svn: 135082

They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

llvm-svn: 135081

llvm-svn: 135077

llvm-svn: 135076

llvm-svn: 135071

The immediate is of limited range and the operand type should reflect that.

llvm-svn: 135066

llvm-svn: 135063

Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.

Add some tests for the diagnostics we do want.

llvm-svn: 135055

llvm-svn: 135052

Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.

llvm-svn: 135049

llvm-svn: 135047

Update the debug output interface for MCParsedAsmOperand to have a print()
method which takes an output stream argument, an << operator which invokes
the print method using the given stream, and a dump() method which prints
the operand to the dbgs() stream. This makes the interface more consistent
with the rest of LLVM, and more convenient to use at the debugger command
line.

llvm-svn: 135043