options to llvm-build, so the all-targets etc. components are defined properly.

llvm-svn: 144255

handle defining the "magic" target related components (like native,
nativecodegen, and engine).
 - We still require these components to be in the project (currently in
   lib/Target) so that we have a place to document them and hopefully make it
   more obvious that they are "magic".

llvm-svn: 144253

change the generated library .a file name once we fully switch over, but
simplifies how we treat these targets without requiring more special casing
(since their library group name and the codegen library name currently map to
the same "llvm-config" style component name).

llvm-svn: 144251

 - Gives us a place to hang target specific metadata (like whether the target has a JIT).

llvm-svn: 144250

llvm-svn: 144244

rdar://10422955

llvm-svn: 144242

llvm-svn: 144241

rdar://10418009

llvm-svn: 144213

llvm-svn: 144212

llvm-svn: 144211

llvm-svn: 144187

Enable execution dependency fix pass for YMM registers when AVX2 is enabled. Add AVX2 logical operations to list of replaceable instructions.

llvm-svn: 144179

llvm-svn: 144176

llvm-svn: 144174

remove a fair number of unnecessary materialized constants.
rdar://10412592

llvm-svn: 144163

llvm-svn: 144154

Patch by Jack Carter.

llvm-svn: 144139

llvm-svn: 144123

No functional change intended.

llvm-svn: 144122

Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.

llvm-svn: 144102

When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses

llvm-svn: 144100

implements unaligned loads and stores with assembler macro-instructions
ulw, usw, ulh, ulhu, ush, and this patch emits corresponding instructions
instead of these macros. Since each unaligned load/store is expanded
into two corresponding loads/stores where offset for second load/store is
modified by +3 (for words) or +1 (for halfwords).

Patch by Petar Jovanovic and Sasa Stankovic.

llvm-svn: 144081

llvm-svn: 144071

llvm-svn: 144057

Add x86 isel logic and patterns to match movlps from clang generated IR for _mm_loadl_pi(). rdar://10134392, rdar://10050222

llvm-svn: 144052

callee's responsibility to sign or zero-extend the return value.  The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).

llvm-svn: 144047

llvm-svn: 144021

llvm-svn: 144019

and add Mips64's version too.

llvm-svn: 144018

registers.

llvm-svn: 144017

floating pointer registers.

llvm-svn: 144016

As a side effect hex is printed lowercase instead of uppercase now.

llvm-svn: 144013

llvm-svn: 144012

The xorps instruction is smaller than pxor, so prefer that encoding.

The ExecutionDepsFix pass will switch the encoding to pxor and xorpd
when appropriate.

llvm-svn: 143996

llvm-svn: 143994

llvm-svn: 143993

is used to save va_arg or byval arguments passed in registers.

llvm-svn: 143992

llvm-svn: 143991

when shift amount is larger than 32.

llvm-svn: 143990

instruction definitions.

llvm-svn: 143989