that they are dead.

llvm-svn: 99000

override prefix and only the r/m16 forms should have had that.  Also for variant
one, the AT&T syntax, added suffixes to all forms.  Also added the missing
64-bit form for 'CRC32 r64, r/m8'.  Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.

llvm-svn: 98980

MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher.

llvm-svn: 98972

room for it.  This is in preparation for another patch which is adding NEON
subformats to facilitate disassembly.

llvm-svn: 98967

 - MCAssembler is now object-file independent, although we will surely need more work to fully support ELF/COFF.

llvm-svn: 98955

llvm-svn: 98954

llvm-svn: 98950

MCAssembler: Move ApplyFixup to the TargetAsmBackend, this is a target specific not object writer specific task.

llvm-svn: 98947

llvm-svn: 98941

need them.

llvm-svn: 98937

llvm-svn: 98936

dag isel gen instead of instruction properties.  This
allows the oh-so-useful behavior of matching a variadic
non-root node.

llvm-svn: 98934

llvm-svn: 98932

match.  Jakob, please take a look when you get a chance.

llvm-svn: 98931

can't match or just have no testcases.  Will remove after 
confirmation from dan that they really are dead.

llvm-svn: 98930

llvm-svn: 98928

llvm-svn: 98919

to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.

Now we can change things like this:

 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
-                  [(X86cmp RFP80:$lhs, RFP80:$rhs),
-                   (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+                  [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;

and fix terrible crimes like this:

-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
           (TEST8rr GR8:$src1, GR8:$src1)>;

This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.

llvm-svn: 98903

llvm-svn: 98902

llvm-svn: 98901

llvm-svn: 98889

llvm-svn: 98888

Refactor Reg-Reg copy emission routine for ARM. This makes cross-regclass copies weirdness more straightforward. Also, add GPR <-> SPR copy support.

llvm-svn: 98887

llvm-svn: 98881

were missing it on some movq instructions and were not including the appropriate
PCrel bias.

llvm-svn: 98880

llvm-svn: 98869

llvm-svn: 98866

llvm-svn: 98864

llvm-svn: 98862

No functional changes.

llvm-svn: 98860

temporary workaround for matching inc/dec on x86_64 to the correct instruction.
 - This hack will eventually be replaced with a robust mechanism for handling
   matching instructions based on the available target features.

llvm-svn: 98858

llvm-svn: 98855

files that produce special relocation types where the 
linker changes movq's into lea's.

llvm-svn: 98839

llvm-svn: 98835

intrinsics.  The intrinsic lookup code assumes that this check has been done
and assumes the names are at least 6 characters long.  Valgrind complained
about this.  pr6638.

llvm-svn: 98831

llvm-svn: 98819

llvm-svn: 98810

MC/Darwin: Add a new target hook for whether the target uses "reliable" symbol differences, basically whether the assembler should attempt to understand atoms when using scattered symbols.

Also, avoid some virtual call overhead.

llvm-svn: 98789

X86 address mode matching code MatchAddressRecursively does some aggressive hack which require doing a RAUW. It may end up deleting some SDNode up stream. It should avoid referencing deleted nodes.

llvm-svn: 98780

There is a better way coming up.

llvm-svn: 98777