llvm-svn: 85355

use it to control tail merging when there is a tradeoff between performance
and code size.  When there is only 1 instruction in the common tail, we have
been merging.  That can be good for code size but is a definite loss for
performance.  Now we will avoid tail merging in that case when the
optimization level is "Aggressive", i.e., "-O3".  Radar 7338114.

Since the IfConversion pass invokes BranchFolding, it too needs to know
the optimization level.  Note that I removed the RegisterPass instantiation
for IfConversion because it required a default constructor.  If someone
wants to keep that for some reason, we can add a default constructor with
a hard-wired optimization level.

llvm-svn: 85346

llvm-svn: 85335

default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.

llvm-svn: 85333

llvm-svn: 85299

BL_pred and BLr9_pred.

llvm-svn: 85297

instruction format that already takes care of setting this.

llvm-svn: 85280

for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.

llvm-svn: 85271

llvm-svn: 85255

llvm-svn: 85235

llvm-svn: 85186

Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.

llvm-svn: 85184

llvm-svn: 85178

bits.  Johnny, please review -- I do not have a good track record of getting
these right.

llvm-svn: 85173

Patch by Johnny Chen.

llvm-svn: 85169

bits.  Patch by Johnny Chen.

llvm-svn: 85167

llvm-svn: 85127

llvm-svn: 85065

llvm-svn: 85064

llvm-svn: 85049

llvm-svn: 85048

VISIBILITY_HIDDEN removal.

llvm-svn: 85043

Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.

llvm-svn: 85042

llvm-svn: 84986

can access the hi regs. Our prologue and epilogue code doesn't know how to
properly handle save/restore of the hi regs, so things go badly when we alloc
them.

llvm-svn: 84982

llvm-svn: 84977

Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.

llvm-svn: 84911

llvm-svn: 84868

Move if-conversion before post-regalloc scheduling so the predicated instruction get scheduled properly.

llvm-svn: 84843

Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit.

llvm-svn: 84842

llvm-svn: 84832

llvm-svn: 84831

llvm-svn: 84813

llvm-svn: 84798

for a few bugs.

llvm-svn: 84791

llvm-svn: 84785

immediate operands when they will fit into the using instruction.

llvm-svn: 84778

Patch by Johnny Chen.

llvm-svn: 84767

llvm-svn: 84766

llvm-svn: 84751