Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.

llvm-svn: 75900

llvm-svn: 75312

Remove TargetInstrInfo::CommuteChangesDestination and added findCommutedOpIndices which returns the operand indices which are swapped (when applicable). This allows for some code clean up and future enhancements.

llvm-svn: 75264

CommuteChangesDestination() should check if to-be-commuted instruction defines any register. Also teaches the default commuteInstruction() to commute instruction without definitions (e.g. X86::test / ARM::tsp).

llvm-svn: 74602

booleans. This gives a better indication of what the "addReg()" is
doing. Remembering what all of those booleans mean isn't easy, especially if you
aren't spending all of your time in that code.

I took Jakob's suggestion and made it illegal to pass in "true" for the
flag. This should hopefully prevent any unintended misuse of this (by reverting
to the old way of using addReg()).

llvm-svn: 71722

llvm-svn: 63599

parts, and add target-independent code to add/preserve
MachineMemOperands.

llvm-svn: 60488

isReg, etc., from isRegister, etc.

llvm-svn: 57006

isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189

llvm-svn: 56097

Convert uses of std::vector in TargetInstrInfo to SmallVector.  This change had to be propoagated down into all the targets and up into all clients of this API.

llvm-svn: 54802

MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.

llvm-svn: 53212

llvm-svn: 52308

Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented

llvm-svn: 49809

llvm-svn: 48995

machine instr will change its definition register.

llvm-svn: 47166

llvm-svn: 47058

llvm-svn: 47043

Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695

over to using them, instead of diddling Flags directly.  Change the
various flags from const variables to enums.

llvm-svn: 45677

that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.

llvm-svn: 45674

a header file from libcodegen.  This violates a layering order: codegen
depends on target, not the other way around.  The fix to this is to 
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen.  It is defined in libcodegen, where 
the base is not.

llvm-svn: 45475

e.g. MO.isMBB() instead of MO.isMachineBasicBlock().  I don't plan on 
switching everything over, so new clients should just start using the 
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(), 
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.

llvm-svn: 45464

  - Eliminate the static "print" method for operands, moving it
    into MachineOperand::print.
  - Change various set* methods for register flags to take a bool
    for the value to set it to.  Remove unset* methods.
  - Group methods more logically by operand flavor in MachineOperand.h

llvm-svn: 45461

Use MachineOperand::getImm instead of MachineOperand::getImmedValue.  Likewise setImmedValue -> setImm

llvm-svn: 45453

llvm-svn: 45418

isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.

llvm-svn: 41958

llvm-svn: 37960

llvm-svn: 37891

llvm-svn: 37528

llvm-svn: 37341

llvm-svn: 37307

llvm-svn: 37139

llvm-svn: 37138

llvm-svn: 37124

llvm-svn: 37123

llvm-svn: 32366

llvm-svn: 32352

llvm-svn: 32098

llvm-svn: 32033