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  1. Feb 02, 2012
    • Andrew Trick's avatar
      Instruction scheduling itinerary for Intel Atom. · 8523b16f
      Andrew Trick authored
      Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.
      
      Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.
      
      Adds a test to verify that the scheduler is working.
      
      Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.
      
      Patch by Preston Gurd!
      
      llvm-svn: 149558
      8523b16f
    • Jakob Stoklund Olesen's avatar
      c7024a48
    • Jakob Stoklund Olesen's avatar
      Specify SubRegIndex components on the index itself. · 21231609
      Jakob Stoklund Olesen authored
      It is simpler to define a composite index directly:
      
        def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>;
        def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>;
      
      Than specifying the composite indices on each register:
      
        CompositeIndices = [(ssub_2 dsub_1, ssub_0),
                            (ssub_3 dsub_1, ssub_1)] in ...
      
      This also makes it clear that SubRegIndex composition is supposed to be
      unique.
      
      llvm-svn: 149556
      21231609
  2. Feb 01, 2012
  3. Jan 31, 2012
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