Skip to content
  1. Feb 02, 2012
    • Andrew Trick's avatar
      Instruction scheduling itinerary for Intel Atom. · 8523b16f
      Andrew Trick authored
      Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.
      
      Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.
      
      Adds a test to verify that the scheduler is working.
      
      Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.
      
      Patch by Preston Gurd!
      
      llvm-svn: 149558
      8523b16f
  2. Oct 23, 2011
  3. Oct 14, 2011
  4. Oct 08, 2011
    • Jakob Stoklund Olesen's avatar
      Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies. · 729abd36
      Jakob Stoklund Olesen authored
      In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
      instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
      target all GR8 registers, only those in GR8_NOREX.
      
      TO enforce this, we ensure that all instructions using the
      EXTRACT_SUBREG are GR8_NOREX constrained.
      
      This fixes PR11088.
      
      llvm-svn: 141499
      729abd36
  5. Oct 02, 2011
  6. Sep 11, 2011
  7. Apr 15, 2011
  8. Dec 20, 2010
    • Chris Lattner's avatar
      Change the X86 backend to stop using the evil ADDC/ADDE/SUBC/SUBE nodes (which · 846c20d4
      Chris Lattner authored
      their carry depenedencies with MVT::Flag operands) and use clean and beautiful
      EFLAGS dependences instead.
      
      We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs
      (which is what requires the previous scheduler change) and change X86 ISelLowering
      to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes.
      
      With the previous series of changes, this causes no changes in the testsuite, woo.
      
      llvm-svn: 122213
      846c20d4
  9. Dec 05, 2010
    • Chris Lattner's avatar
      it turns out that when ".with.overflow" intrinsics were added to the X86 · 364bb0a0
      Chris Lattner authored
      backend that they were all implemented except umul.  This one fell back
      to the default implementation that did a hi/lo multiply and compared the
      top.  Fix this to check the overflow flag that the 'mul' instruction
      sets, so we can avoid an explicit test.  Now we compile:
      
      void *func(long count) {
            return new int[count];
      }
      
      into:
      
      __Z4funcl:                              ## @_Z4funcl
      	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
      	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
      	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
      	seto	%cl                     ## encoding: [0x0f,0x90,0xc1]
      	testb	%cl, %cl                ## encoding: [0x84,0xc9]
      	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
      	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
      	jmp	__Znam                  ## TAILCALL
      
      instead of:
      
      __Z4funcl:                              ## @_Z4funcl
      	movl	$4, %ecx                ## encoding: [0xb9,0x04,0x00,0x00,0x00]
      	movq	%rdi, %rax              ## encoding: [0x48,0x89,0xf8]
      	mulq	%rcx                    ## encoding: [0x48,0xf7,0xe1]
      	testq	%rdx, %rdx              ## encoding: [0x48,0x85,0xd2]
      	movq	$-1, %rdi               ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff]
      	cmoveq	%rax, %rdi              ## encoding: [0x48,0x0f,0x44,0xf8]
      	jmp	__Znam                  ## TAILCALL
      
      Other than the silly seto+test, this is using the o bit directly, so it's going in the right
      direction.
      
      llvm-svn: 120935
      364bb0a0
  10. Oct 08, 2010
    • Chris Lattner's avatar
      fix a subtle bug I introduced in my refactoring, where we stopped preferring · 35e6ce47
      Chris Lattner authored
      the i8 versions of instructions in some cases.  In test6, we started 
      generating:
      
      	cmpq	$0, -8(%rsp)            ## encoding: [0x48,0x81,0x7c,0x24,0xf8,0x00,0x00,0x00,0x00]
                                              ## <MCInst #478 CMP64mi32
                                              ##  <MCOperand Reg:114>
                                              ##  <MCOperand Imm:1>
                                              ##  <MCOperand Reg:0>
                                              ##  <MCOperand Imm:-8>
                                              ##  <MCOperand Reg:0>
                                              ##  <MCOperand Imm:0>>
      
      instead of:
      
      	cmpq	$0, -8(%rsp)            ## encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
                                              ## <MCInst #479 CMP64mi8
                                              ##  <MCOperand Reg:114>
                                              ##  <MCOperand Imm:1>
                                              ##  <MCOperand Reg:0>
                                              ##  <MCOperand Imm:-8>
                                              ##  <MCOperand Reg:0>
                                              ##  <MCOperand Imm:0>>
      
      Fix this and add some comments.
      
      llvm-svn: 116053
      35e6ce47
  11. Oct 07, 2010
  12. Oct 06, 2010
  13. Oct 05, 2010
Loading