Update dwarf writer to only emit one DW_TAG_compile_unit per .o file. 

llvm-svn: 74449

llvm-svn: 74448

an individual exhaustive evaluation reflects only the exit value
implied by an individual exit, which may differ from the actual
exit value of the loop if there are other exits. This fixes PR4477.

llvm-svn: 74447

Not sure I understand how the temp register gets used,
but this fixes a bug and introduces no regressions.

llvm-svn: 74446

Add some tests of advanced TableGen list functionality.

llvm-svn: 74445

Implement !cast<string>.

llvm-svn: 74444

Improve TableGen error reporting.

llvm-svn: 74443

Not doing so causes some unittests to fail, because CurSection is uninitialized.

llvm-svn: 74442

llvm-svn: 74441

llvm-svn: 74440

llvm-svn: 74439

Also don't call finalizers for LoopPass if initialization was not called.
Add a unittest that tests that these methods are called, in the proper
order, and the correct number of times.

llvm-svn: 74438

(otherwise harmless) uninitialized value warnings that
Duncan found with gcc-4.4.

llvm-svn: 74437

fence-atomic-fence down to just the atomic op.  This is possible thanks to
X86's relatively strong memory model, which guarantees that locked instructions
(which are used to implement atomics) are implicit fences.

llvm-svn: 74435

llvm-svn: 74430

Add processor descriptions for Istanbul and Shanghai.

llvm-svn: 74429

Fix a subtarget feature bug.

llvm-svn: 74428

Add more vector ValueTypes for AVX and other extended vector instruction
sets.

llvm-svn: 74427

llvm-svn: 74426

Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.

llvm-svn: 74423

llvm-svn: 74422

to make sure ThumbRegisterInfo.cpp are compiled and linked in.
Patch by Xerxes.

llvm-svn: 74421

After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420

Implemented by making lib/CompilerDriver a shared library that holds all the
global static data (CommandLine options, plugin registry) that we unfortunately
have to live with.

llvm-svn: 74417

llvm-svn: 74416

llvm-svn: 74415

llvm-svn: 74402

llvm-svn: 74401

llvm-svn: 74400

doesn't have an IV-based operand. This fixes PR4471.

llvm-svn: 74399

LoopInfo will handle removing it from the Loop, as well as updating
its own tables.

llvm-svn: 74398

when one of them can be converted to a trivial icmp and conditional
branch.

This addresses what is essentially a phase ordering problem.
SimplifyCFG knows how to do this transformation, but it doesn't do so
if the primary block has any instructions in it other than an icmp and
a branch. In the given testcase, the block contains other instructions,
however they are loop-invariant and can be hoisted. SimplifyCFG doesn't
have LoopInfo though, so it can't hoist them. And, it's important that
the blocks be merged before LoopRotation, as it doesn't support
multiple-exit loops.

llvm-svn: 74396

llvm-svn: 74395

llvm-svn: 74394

of a team of individual allocations and a team of std::maps.

llvm-svn: 74393

llvm-svn: 74392

llvm-svn: 74391

llvm-svn: 74389

llvm-svn: 74385

llvm-svn: 74384