llvm-svn: 129883

the spilled register.

This is quite common on ARM now that some stores have early-clobber defines.

llvm-svn: 129714

The rematerialized instruction may require a more constrained register class
than the register being spilled. In the test case, the spilled register has been
inflated to the DPR register class, but we are rematerializing a load of the
ssub_0 sub-register which only exists for DPR_VFP2 registers.

The register class is reinflated after spilling, so the conservative choice is
only temporary.

llvm-svn: 128610

The spill weight is not recomputed for an unspillable register - it stays infinite.

llvm-svn: 128490

llvm-svn: 128469

This may eliminate some uses of the spilled registers, and we don't want to
insert reloads for that.

llvm-svn: 128468

The instruction to be rematerialized may not be the one defining the register
that is being spilled. The traceSiblingValue() function sees through sibling
copies to find the remat candidate.

llvm-svn: 128449

The main register class may have been inflated by live range splitting, so that
register class is not necessarily valid for the snippet instructions.

Use the original register class for the stack slot interval.

llvm-svn: 128351

This can happen when multiple sibling registers are spilled after live range
splitting.

llvm-svn: 127965

llvm-svn: 127964

llvm-svn: 127959

Stack slot real estate is virtually free compared to registers, so it is
advantageous to spill earlier even though the same value is now kept in both a
register and a stack slot.

Also eliminate redundant spills by extending the stack slot live range
underneath reloaded registers.

This can trigger a dead code elimination, removing copies and even reloads that
were only feeding spills.

llvm-svn: 127868

I have convinced myself that it can only happen when a phi value dies. When it
happens, allocate new virtual registers for the components.

llvm-svn: 127827

After live range splitting, an original value may be available in multiple
registers. Tracing back through the registers containing the same value, find
the best place to insert a spill, determine if the value has already been
spilled, or discover a reaching def that may be rematerialized.

This is only the analysis part. The information is not used for anything yet.

llvm-svn: 127698

Remove the unused reserved_ bit vector, no functional change intended.

This doesn't break 'svn blame', this file really is all my fault.

llvm-svn: 127607

This allows the allocator to free any resources used by the virtual register,
including physical register assignments.

llvm-svn: 127560

llvm-svn: 127530

Live range splitting can create a number of small live ranges containing only a
single real use. Spill these small live ranges along with the large range they
are connected to with copies. This enables memory operand folding and maximizes
the spill to fill distance.

Work in progress with known bugs.

llvm-svn: 127529

This makes it possible to register delegates and get callbacks when the spiller
edits live ranges.

llvm-svn: 127389

llvm-svn: 127388

This will we used for keeping register allocator data structures up to date
while LiveRangeEdit is trimming live intervals.

llvm-svn: 127300

llvm-svn: 127181

register.

This avoids some silly stack slot shuffling when both sides of a copy get
spilled.

llvm-svn: 126353

llvm-svn: 126258

This almost guarantees that the COPY will be coalesced.

llvm-svn: 125140

The target hook doesn't know how to do that. (Neither do I).

llvm-svn: 125108

physical register numbers.

This makes the hack used in LiveInterval official, and lets LiveInterval be
oblivious of stack slots.

The isPhysicalRegister() and isVirtualRegister() predicates don't know about
this, so when a variable may contain a stack slot, isStackSlot() should always
be tested first.

llvm-svn: 123128

llvm-svn: 122135

use before rematerializing the load.

This allows us to produce:

    addps	LCPI0_1(%rip), %xmm2

Instead of:

    movaps	LCPI0_1(%rip), %xmm3
    addps	%xmm3, %xmm2

Saving a register and an instruction. The standard spiller already knows how to
do this.

llvm-svn: 122133

createMachineVerifierPass and MachineFunction::verify.

The banner is printed before the machine code dump, just like the printer pass.

llvm-svn: 122113

The spiller should only spill. The register allocator will drive live range
splitting, it has the needed information about register pressure and
interferences.

llvm-svn: 121590

live ranges for the spill register are also defined at the use slot instead of
the normal def slot.

This fixes PR8612 for the inline spiller. A use was being allocated to the same
register as a spilled early clobber def.

This problem exists in all the spillers. A fix for the standard spiller is
forthcoming.

llvm-svn: 119182

constant loads.

llvm-svn: 118741

benchmarks hitting an assertion.
Adds LiveIntervalUnion::collectInterferingVRegs.
Fixes "late spilling" by checking for any unspillable live vregs among
all physReg aliases.

llvm-svn: 118701

llvm-svn: 118661

This way, InlineSpiller does the same amount of splitting as the standard
spiller. Splitting should really be guided by the register allocator, and
doesn't belong in the spiller at all.

llvm-svn: 118216

llvm-svn: 118193

give them individual stack slots once the are actually spilled.

llvm-svn: 117945

llvm-svn: 117761

llvm-svn: 117629